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PDF M3488Q1 Data sheet ( Hoja de datos )

Número de pieza M3488Q1
Descripción 256 x 256 DIGITAL SWITCHING MATRIX
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M3488
256 x 256 DIGITAL SWITCHING MATRIX
. 256 INPUT AND 256 OUTPUT CHANNEL
. CMOS DIGITAL SWITCHING MATRIX COM-
PATIBLE WITH M088
BUILDING BLOCK DESIGNED FOR LARGE
. CAPACITY ELECTRONIC EXCHANGES, SUB-
SYSTEMS AND PABX
NO EXTRA PIN NEEDED FOR NOT-BLOCK-
ING SINGLE STAGE AND HIGHER CAPACITY
SYNTHESIS BLOCKS (512 or 1024 channels)
. EUROPEAN TELEPHONE STANDARD COM-
PATIBLE (32 serial channels per frame)
. PCM INPUTS AND OUTPUTS MUTUALLY
COMPATIBLE
. ACTUAL INPUT-OUTPUT CHANNEL CON-
NECTIONS STORED AND MODIFIED VIA AN
ON CHIP 8-BIT PARALLEL MICROPROCES-
SOR INTERFACE
. TYPICAL BIT RATE : 2Mbit/s
. TYPICAL SYNCHRONIZATION RATE : 8KHz
(time frame is 125µs)
. 5V P0WER SUPPLY
. CMOS & TTL INPUT/OUTPUT LEVELS COM-
PATIBLE
. HIGH DENSITY ADVANCED 1.2µm HCMOS3
PROCESS
PRELIMINARY DATA
DIP40
PQFP44
ORDERING NUMBERS:
M3488B1
M3488Q1
Main instructions controlled by the microproc-
essor interface
. CHANNEL CONNECTION/DISCONNECTION
. OUTPUT CHANNEL DISCONNECTION
. INSERTION OF A BYTE ON A PCM OUTPUT
CHANNEL/DISCONNECTION
. TRANSFER TO THE MICROPROCESSOR OF
A SINGLE PCM OUTPUT CHANNEL SAMPLE
. TRANSFER TO THE MICROPROCESSOR OF
. A SINGLE OUTPUT CHANNEL CONTROL
WORD
TRANSFER TO THE MICROPROCESSOR OF
A SELECTED 0 CHANNEL PCM INPUT DATA
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
VO
IO
Ptot
Tstg
Top
Parameter
Supply Voltage
Input Voltage
Off State Output Voltage
Current at Digital Outputs
Total Package Power Dissipation
Storage Temperature Range
Operating Temperature Range
Test Conditions
-0.3 to 7
-0.3 to VCC+0.3
-0.3 to VCC+0.3
30
1.5
-65 to 150
0 to 70
Unit
V
V
V
mA
W
°C
°C
Stresses above those l isted under ” Absolute Maximum Ratings” may cause permanent damage to the devi ce. This is a stress
rati ngs only and functional operation of the device at these or any other conditions above those indicated in the operating con-
ditions of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect devi ce
reliabili ty.
November 1994
1/18
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1 page




M3488Q1 pdf
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC Supply Voltage
Vi Input Voltage
VO Off State Input Voltage
CLOCK Input Clock Frequency
Freq.
SYNC Freq. Input Synchronization Frequency
Top Operating Temperature
M3488
Value
4.75 to 5.25
0 to 5.25
0 to 5.25
4.096
8
0 to 70
Unit
V
V
V
MHz
KHz
°C
CAPACITANCES (measurement freq. = 1MHz; Top = 0 to 70°C; unused pins tied to VSS)
Symbol
Parameter
Pins (*)
Min. Typ. Max.
CI Input Capacitance
6 to 15; 26 to 30; 32 to 36
5
CI/O I/O Capacitance
20 to 24
15
CO Output Capacitance
1 to 4; 17 to 19; 25; 37 to 40
10
Unit
pF
pF
pF
D.C. ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C, VCC = 5V ±5%)
All D.C. characteristics are valid 250µs after VCC and clock have been applied.
Symbol
VILC
VIHC
VIL
VIH
VOH
IOH
VOL
IOL
IIL
IDL
ICC
Parameter
Clock Input Low Level
Clock Input High Level
Input Low Level
Input High Level
Output High Voltage (Level)
Output High Current
Output Low Voltage (Level)
Output Low Current
Input Leakage Current
Data Bus Leakage Current
Supply Current
Pins (*)
6
6
7 to 15
20 to 24
26 to 30
32 to 36
7 to 15
20 to 24
26 to 30
32 to 36
17 to 25
1 to 4
37 to 40
17 to 25
Test Condition
IOH = 5mA
VOH = 2.4V
IOL = 5mA
VOL = 0.4V
6 to 15
26 to 30
32 to 36
17 to 24
16
VIN = 0 to VCC
VIN = 0 to VCC
VCC applied; Pins 35
and 36 tied to VCC,
after Device Initialization
Clock Freq. = 4.096MHz
Min.
-0.3
2.4
-0.3
2
2.4
5
5
Typ.
15
(*) The pin number is referred to the DIP40 version.
Max.
0.8
VCC
0.8
VCC
0.4
5
±5
30
Unit
V
V
V
V
V
mA
V
mA
µA
µA
mA
5/18

5 Page





M3488Q1 arduino
M3488
PIN DESCRIPTION
D7 to D0
Data bus pins. The bidirectional bus is usedto trans-
fer dataand instructions to/fromthe microprocessor.
D0 is the least significant digit. The output bus is 8
bits wide ; input is only 5 bits wide. (D4 to D0)
The bus is tristate and cannot be used while RESET
is held low.
The meaning of input data, such as bus or channel
numbers, and of expected output data is specified
in detail by the instruction description. (Pagg. 12-14)
C/D (pin 30)
Input control pin, select pin. In a write operation
C/D = 0 qualifies any bus content as data, while
C/D = 1 qualifies it as an opcode. In a read operation
OR1 is selected by C/D = 0, OR2 by C/D = 1.
A1, S1, A2, S2
Address select or match pins. In a multi-chip con-
figuration (e.g. a single stage matrix expansion), us-
ing the same CS pins, the match condition (A1 = S1
and A2 = S2) leaves the commandinstruction as de-
fined; on the contrary the mismatch condition modi-
fies the execution as follows : instructions 1 and 3
are reversed to channeldisconnection, instruction 5
is unaffected, instructions 2-4-6 are cancelled (not
executed).
Bus reading takes place only on match condition,
instruction flow is in any case affected.
Eachpins couple is commutative : in a multichip con-
figuration pins S1 and S2 give a hard-wired address
selection for individual matrixes, while in single con-
figuration S1 and A1 or S2 and A2 are normally
tied together.
CS1, CS2
Commutative chip select pins. They enable the de-
vice to perform valid read/write operations (active
low). Two pins allow row/column selection with dif-
ferent types of microprocessors ; normally one is
tied to ground.
WR
Pin WR, when CS1 and CS2 are low, enables data
transfer from microprocessor to the device. Data or
opcode and controls are latchedon WR rising edge.
Becauseof internal clock resynchronizationone sin-
gle additionalrequirement is recommended in order
to produce a simultaneous instruction execution in
a multichip configuration: WR rising edge has to be
20 to 20 + tWL(CK) nsec late relative to clock falling
edge.
RD
When CS1 andCS2 are low and match condition ex-
ists, a low level on RD enables a register OR1 or
OR2 read operation, through the bidirectional bus.
In addition, the rising edge of RD latches C/D and
the match condition pins in order to direct the inter-
nal flow of operations. Because of internal clock
resynchronization, one single additional require-
ment is recommended in order to produce a simul-
taneousinstruction flow in a multichip configuration:
the RD rising edge has to be 20 to 20 + tWL(CK) nsec
late relative to clock falling edge.
DR
Data ready. Normally high, DR output pin goes low
to tell the microprocessor that :
a) the instruction code was found to be invalid ;
b) executing instruction 5 an active output channel
was found in the whole matrix array, that is a CM
word not all ”ones” was found in a configuration of
devices sharing the same CS pins ;
c) executing instruction 6 ”0 channel extraction” took
place and OR2 was loaded with total number of
messages inserted on 0 time slot.
DR is active low about two clock cycles in case b
and c ; in case a it is left low until a valid instruction
code is supplied.
RESET
RESET control pin is normally used at the very be-
ginning to initialize the device or the network. Any
logical status is reset andCM is set to all ”ones” after
RESET going low.
The internal initialization routine takes one time
frame whatever the RESET width on low level (mini-
mum one cycle roughly), but it is repeatedan integer
number of time frames as long as RESET is found
low during 0 time slot.
Initialization pulls the interface bus immediately to a
high impedance state. After the CM has been set to
all ”ones” the PCM output channels are also set to
high impedance state.
CLOCK
Input master clock. Typical frequency is 4.096MHz.
First division gives an internal clock controlling the
input and output channels bit rate.
SYNC
Input synchronization signal is active low. Typical
frequency is 8kHz.
11/18

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