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PDF M30LW128D Data sheet ( Hoja de datos )
| Número de pieza | M30LW128D | |
| Descripción | 128 Mbit (two 64Mbit / x8/x16 / Uniform Block / Flash Memories) 3V Supply / Multiple Memory Product | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M30LW128D
128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories)
3V Supply, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY
s TWO M58LW064D 64Mbit FLASH MEMORIES
STACKED IN A SINGLE PACKAGE
s WIDE x8 or x16 DATA BUS for HIGH
BANDWIDTH
s SUPPLY VOLTAGE
– VDD = 2.7 to 3.6V for Program, Erase and
Read operations
– VDDQ = 1.8 to VDD for I/O buffers
s ACCESS TIME
– Random Read 110ns
– Page Mode Read 110/25ns
s PROGRAMMING TIME
– 16 Word Write Buffer
– 16µs Word effective programming time
s 128 UNIFORM 64 KWord/128KByte MEMORY
BLOCKS
s BLOCK PROTECTION/ UNPROTECTION
s PROGRAM and ERASE SUSPEND
s 128 bit PROTECTION REGISTER
s COMMON FLASH INTERFACE
s 100, 000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code M30LW128D: 8817h
Figure 1. Packages
TSOP56 (N)
14 x 20 mm
TBGA
TBGA64 (ZA)
10 x 13mm
FBGA
LFBGA88 (ZE)
8 x 10mm
February 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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1 page  
M30LW128D
SUMMARY DESCRIPTION
The M30LW128D is a 128 Mbit device that is com-
posed of two separate 64 Mbit M58LW064D Flash
memories. The device can be erased electrically
at block level and programmed in-system using a
2.7V to 3.6V (VDD) supply for the circuitry and a
1.8V to VDD (VDDQ) supply for the Input/Output
pins.
The bus width can be configured for x8 or x16 for
the devices available in the TSOP56 (14 x 20 mm)
and TBGA64 (10x13mm, 1mm pitch) packages.
The bus width is set to x16 for the devices avail-
able in the LFBGA88 (8x10mm, 0.8mm pitch)
package.
Each internal M58LW064D has 3 Chip Enable sig-
nals to allow up to 4 memories to be connected to-
gether without the use of additional glue logic. In
this way the address space is contiguous and the
microprocessor only requires one Chip Enable, E,
to control both memories.
The device is divided into 128 blocks of 1Mbit (2 x
64 x 1Mb) that can be erased independently so it
is possible to preserve valid data while old data is
erased. Program and Erase commands are written
to the Command Interface of the device. An on-
chip Program/Erase Controller (P/E.C) simplifies
the process of programming or erasing the device
by taking care of all of the special operations that
are required to update the memory contents. The
end of a Program or Erase operation can be de-
tected and any error conditions identified in the
Status Register. The command set required to
control the device is consistent with JEDEC stan-
dards.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
Individual block protection against Program or
Erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera-
tions are blocked when the Program Erase Enable
input VPEN is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the enabled memory and to set
the device in power-down mode.
The STS signal is an open drain output that can be
used to identify the Program/Erase Controller sta-
tus. It can be configured in two modes: Ready/
Busy mode where a static signal indicates the sta-
tus of the P/E.C, and Status mode where a pulsing
signal indicates the end of a Program or Block
Erase operation. In both modes it can be used as
a system interrupt signal, useful for saving CPU
time. The STS signal is only available with the
TSOP56 and TBGA64 packages.
Each memory includes a 128 bit Protection Regis-
ter. The Protection Register is divided into two 64
bit segments, the first one is written by the manu-
facturer (contact STMicroelectronics to define the
code to be written here), while the second one is
programmable by the user. The user programma-
ble segment can be locked.
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5 Page 
M30LW128D
s Status - the pin gives a pulsing signal to indicate
the end of a Program or Block Erase operation.
After power-up or reset the STS pin is configured
in Ready/Busy mode. The pin can be configured
for Status mode using the Configure STS com-
mand.
When the Program/Erase Controller is idle, or sus-
pended, STS can float High through a pull-up re-
sistor. The use of an open-drain output allows the
STS pins from several devices to be connected to
a single pull-up resistor (a Low will indicate that
one, or more, of the memories is busy).
STS is not Low during a reset unless the reset was
applied when the Program/Erase controller was
active.
The STS signal is not available with the LFBGA88
package.
Program/Erase Enable (VPEN). The Program/
Erase Enable input, VPEN, is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the device. It is the
main power supply for all operations (Read, Pro-
gram and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
It is recommended to power-up and power-down
VDD and VDDQ together to avoid any condition that
would result in data corruption.
VSS Ground. Ground, VSS, is the reference for
the core power supply. It must be connected to the
system ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS.
Note: Each device in a system should have
VDD and VDDQ decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 10, AC Measurement Load Circuit.
11/57
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| PDF Descargar | [ Datasheet M30LW128D.PDF ] | |
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