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PDF M2V56S40TP Data sheet ( Hoja de datos )

Número de pieza M2V56S40TP
Descripción 256M Synchronous DRAM
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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No Preview Available ! M2V56S40TP Hoja de datos, Descripción, Manual

SDRAM (Rev.1.1)
Single Data Rate
Feb.2000
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20TP is a 4-bank x 16777216-word x 4-bit,
M2V56S30TP is a 4-bank x 8388608-word x 8-bit,
M2V56S40TP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz (-7/-8) , 133MHz
(-6), and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency 100MHz(-7/-8), 133MHz (-6)
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
M2V56S20/30/40TP-6
M2V56S20/30/40TP-7
M2V56S20/30/40TP-8
Max. Frequency
@CL2
100MHz
100MHz
77MHz
Max. Frequency
@CL3
133MHz
100MHz
100MHz
Standard
PC133 (CL3)
PC100 (CL2)
PC100 (CL3)
MITSUBISHI ELECTRIC
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M2V56S40TP pdf
SDRAM (Rev.1.1)
Single Data Rate
Feb.2000
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
BASIC FUNCTIONS
The M2V56S20/30/40TP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command define basic commands
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-
precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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M2V56S40TP arduino
SDRAM (Rev.1.1)
Single Data Rate
Feb.2000
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
CKE CKE
Current State
n-1 n
SELF-
REFRESH*1
H
L
X
H
LH
LH
LH
LH
LL
POWER
DOWN
HX
LH
LL
ALL BANKS
IDLE*2
H
H
H
L
HL
HL
HL
HL
HL
LX
ANY STATE
other than
listed above
H
H
L
H
L
H
LL
/CS /RAS /CAS /WE Add
Action
X X X X X INVALID
H X X X X Exit Self-Refresh (Idle after tRC)
L H H H X Exit Self-Refresh (Idle after tRC)
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
X X X X X NOP (Maintain Self-Refresh)
X X X X X INVALID
X X X X X Exit Power Down to Idle
X X X X X NOP (Maintain Power Down)
X X X X X Refer to Function Truth Table
L L L H X Enter Self-Refresh
H X X X X Enter Power Down
L H H H X Enter Power Down
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
X X X X X Refer to Current State =Power Down
X X X X X Refer to Function Truth Table
X X X X X Begin CLK Suspend at Next Cycle*3
X X X X X Exit CLK Suspend at Next Cycle*3
X X X X X Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be
satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MITSUBISHI ELECTRIC
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