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PDF M2V56S40ATP Data sheet ( Hoja de datos )

Número de pieza M2V56S40ATP
Descripción 256M Synchronous DRAM
Fabricantes Mitsubishi 
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SDRAM (Rev.1.01)
Single Data Rate
Jul '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20ATP is a 4-bank x 16777216-word x 4-bit,
M2V56S30ATP is a 4-bank x 8388608-word x 8-bit,
M2V56S40ATP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40ATP achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
M2V56S20/30/40ATP-5
Max. Frequency
@CL2
133 MHz
Max. Frequency
@CL3
166 MHz
Standard
PC133 (CL2)
M2V56S20/30/40ATP-6
100MHz
133 MHz
PC133 (CL3)
M2V56S20/30/40ATP-7
100 MHz
100MHz
PC100 (CL2)
MITSUBISHI ELECTRIC
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M2V56S40ATP pdf
SDRAM (Rev.1.01)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP -5, -6, -7
Jul '01
256M Synchronous DRAM
BASIC FUNCTIONS
The M2V56S20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command define basic commands
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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M2V56S40ATP arduino
SDRAM (Rev.1.01)
Single Data Rate
Jul '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
CKE CKE
Current State
n-1 n
SELF-
REFRESH*1
H
L
X
H
LH
LH
LH
LH
LL
POWER
DOWN
HX
LH
LL
ALL BANKS
IDLE*2
H
H
H
L
HL
HL
HL
HL
HL
LX
ANY STATE
other than
listed above
H
H
L
H
L
H
LL
/CS /RAS /CAS /WE
XXXX
HX XX
L HHH
L HH L
LHL X
L LXX
XXXX
XXXX
XXXX
XXXX
XXXX
L LLH
HX XX
L HHH
L HH L
LHL X
L LXX
XXXX
XXXX
XXXX
XXXX
XXXX
Add Action
X INVALID
X Exit Self-Refresh (Idle after tRC)
X Exit Self-Refresh (Idle after tRC)
X ILLEGAL
X ILLEGAL
X ILLEGAL
X NOP (Maintain Self-Refresh)
X INVALID
X Exit Power Down to Idle
X NOP (Maintain Power Down)
X Refer to Function Truth Table
X Enter Self-Refresh
X Enter Power Down
X Enter Power Down
X ILLEGAL
X ILLEGAL
X ILLEGAL
X Refer to Current State =Power Down
X Refer to Function Truth Table
X Begin CLK Suspend at Next Cycle*3
X Exit CLK Suspend at Next Cycle*3
X Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously .
A minimum setup time must be satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MITSUBISHI ELECTRIC
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