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PDF M2V28S20TP Data sheet ( Hoja de datos )
| Número de pieza | M2V28S20TP | |
| Descripción | 128M Synchronous DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL
interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as
4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20TP,M2V28S30TP,M2V28S40TP achieves very high speed data rates up to 133MHz, and is
suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Icc6
Clock Cycle Time
(Min.)
Active to Precharge Command Period
Row to Column Delay
Access Time from CLK
Ref/Active Command Period
Operation Current
(Max.)
(Single Bank)
Self Refresh Current
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
V28S20
V28S30
V28S40
(Max.)
M2V28S20/30/40TP
-6 -7
-8
7.5ns
10ns 10ns
45ns 50ns
50ns
20ns
5.4ns
67.5ns
20ns
6ns
70ns
20ns
6ns
70ns
120mA 115mA 115mA
130mA
-
120mA
135mA
120mA
135mA
2mA
2mA
2mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
- PC133(-6) supports x4/x8 only. And does not support Low-Power (L) version.
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40TP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
M2V28S20TP/30TP/40TP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1
1 page  
SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
PIN FUNCTION
CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
BA0,1
DQ0-7
Input
Input / Output
DQM
Input
Vdd, Vss
VddQ, VssQ
Power Supply
Power Supply
Master Clock:
All other inputs are referenced to the rising edge of CLK.
Clock Enable:
CKE controls internal clock. When CKE is low, internal clock for the
following cycle is ceased. CKE is also used to select auto /
selfrefresh. After self refresh mode is started, CKE becomes
synchronous input. Self refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable:
When DQM is high in burst write, Din for the current cycle is masked.
When DQM is high in burst read, Dout is disabled at the next but one
cycle.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
MITSUBISHI ELECTRIC
5
5 Page 
SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command Action
PRE -
H X X XX
CHARGING
L H H HX
DESEL NOP (Idle after tRP)
NOP NOP (Idle after tRP)
L H H L BA
TBST ILLEGAL*2
READ /
L H L X BA, CA, A10 WRITE ILLEGAL*2
L L H H BA, RA
ACT ILLEGAL*2
L L H L BA, A10
PRE /
NOP*4 (Idle after tRP)
PREA
L L L HX
Op-Code,
LL LL
Mode-Add
REFA ILLEGAL
MRS ILLEGAL
ROW
H X X XX
ACTIVATING
L H H HX
DESEL NOP (Row Active after tRCD)
NOP NOP (Row Active after tRCD)
L H H L BA
TBST ILLEGAL*2
READ /
L H L X BA, CA, A10
ILLEGAL*2
WRITE
L L H H BA, RA
ACT ILLEGAL*2
L L H L BA, A10
PRE /
PREA ILLEGAL*2
L L L HX
Op-Code,
L L L L Mode-Add
REFA ILLEGAL
MRS ILLEGAL
MITSUBISHI ELECTRIC
11
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| PDF Descargar | [ Datasheet M2V28S20TP.PDF ] | |
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