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PDF M2S12D30TP Data sheet ( Hoja de datos )

Número de pieza M2S12D30TP
Descripción 512M Double Data Rate Synchronous DRAM
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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No Preview Available ! M2S12D30TP Hoja de datos, Descripción, Manual

DDR SDRAM (Rev.1.1)
Feb.ME'0LITE2SCUTBRIISCHI
MITSUBISHI LSIs
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
DESCRIPTION
M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit,
M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and
output data and data strobe are referenced on both edges of CLK. The M2S12D20/30TP achieve
very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
- Commands are entered on each positive CLK edge;
- data and data mask are referenced to both edges of DQS
- 4 bank operations are controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge is controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11-12(x4)/ A0-9,11(x8)
SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
- Low Power for the Self Refresh Current ICC6 :4mA (-75L,-10L)
Operating Frequencies
Speed Grade
-75 / -75L
-10 / -10L
Clock Rate
CL=2 *
CL=2.5 *
100MHz
133MHz
100MHz
125MHz
* CL = CAS(Read) Latency
Contents are subject to change without notice.
MITSUBISHI ELECTRIC
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1 page




M2S12D30TP pdf
DDR SDRAM (Rev.1.1)
Feb.ME'0LITE2SCUTBRIISCHI
MITSUBISHI LSIs
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
BASIC FUNCTIONS
The M2S12D20/30TP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select,
refresh option, and precharge option, respectively. Refer to the command truth table for the
detailed definition of commands.
/CLK
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
define basic commands
/WE
Command
CKE
Refresh Option @refresh command
A10 Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates one row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H in this command, the bank is deactivated after the burst read (auto-
precharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is defined by burst length. When A10 =H in this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H in this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh addresses including bank address are generated
internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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5 Page





M2S12D30TP arduino
DDR SDRAM (Rev.1.1)
Feb.ME'0LITE2SCUTBRIISCHI
MITSUBISHI LSIs
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State CKE n-1 CKE n /CS
SELF-
REFRESHING
H
L
XX
HH
L HL
L HL
L HL
L HL
L LX
POWER H X X
DOWN
L HX
L LX
ALL BANKS
IDLE
H
H
HX
LL
H LH
H LL
H LL
H LL
H LL
L XX
ANY STATE
other than listed
above
H
H
L
HX
LX
HX
L LX
/RAS /CAS /WE Address
Action
Notes
X X X X INVALID
1
X X X X Exit Self-Refresh (Idle after tRC)
1
H H H X Exit Self-Refresh (Idle after tRC)
1
H H L X ILLEGAL
1
H L X X ILLEGAL
1
L X X X ILLEGAL
1
X X X X NOP (Maintain Self-Refresh)
1
X X X X INVALID
X X X X Exit Power Down to Idle
X X X X NOP (Maintain Self-Refresh)
X X X X Refer to Function Truth Table
2
L L H X Enter Self-Refresh
2
X X X X Enter Power Down
2
H H H X Enter Power Down
2
H H L X ILLEGAL
2
H L X X ILLEGAL
2
L X X X ILLEGAL
2
X X X X Refer to Current State =Power Down 2
X X X X Refer to Function Truth Table
X X X X Begin CLK Suspend at Next Cycle
3
X X X X Exit CLK Suspend at Next Cycle
3
X X X X Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. Low to High transition of CKE re-enable CLK and other inputs asynchronously.
A minimum setup time must be satisfied before any command except EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MITSUBISHI ELECTRIC
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