PDF M29W800T Data sheet ( Hoja de datos )

Número de pieza	M29W800T
Descripción	8 Mbit 1Mb x8 or 512Kb x16 / Boot Block Low Voltage Single Supply Flash Memory
Fabricantes	ST Microelectronics
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M29W800T M29W800B 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory M29W800T and M29W800B are replaced respectively by the M29W800AT and M29W800AB 2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS FAST ACCESS TIME: 90ns FAST PROGRAMMING TIME – 10µs by Byte / 20µs by Word typical PROGRAM/ERASE CONTROLLER (P/E.C.) – Program Byte-by-Byte or Word-by-Word – Status Register bits and Ready/Busy Output MEMORY BLOCKS – Boot Block (Top or Bottom location) – Parameter and Main blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTI BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend LOW POWER CONSUMPTION – Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION – Defectivity below 1ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Device Code, M29W800T: 00D7h – Device Code, M29W800B: 005Bh DESCRIPTION The M29W800 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byteor Word- by-Word basis using only a single 2.7V to 3.6V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against pro- graming and erase on programming equipment, NOT FOR NEW DESIGN TSOP48 (N) 12 x 20 mm 44 1 SO44 (M) Figure 1. Logic Diagram VCC 19 A0-A18 15 DQ0-DQ14 W DQ15A–1 M29W800T E M29W800B BYTE G RB RP VSS AI02178 June 1999 This is information on a product still in production but not recommended for new designs. 1/33 1 page M29W800T, M29W800B Figure 3B. Bottom Boot Block Memory Map and Block Address Table BOTTOM BOOT BLOCK Word-Wide Byte-Wide 7FFFFh FFFFFh 78000h 77FFFh F0000h EFFFFh 70000h 6FFFFh E0000h DFFFFh 68000h 67FFFh D0000h CFFFFh 60000h 5FFFFh C0000h BFFFFh 58000h 57FFFh B0000h AFFFFh 50000h 4FFFFh A0000h 9FFFFh 48000h 47FFFh 90000h 8FFFFh 40000h 3FFFFh 80000h 7FFFFh 38000h 37FFFh 70000h 6FFFFh 30000h 2FFFFh 60000h 5FFFFh 28000h 27FFFh 50000h 4FFFFh 20000h 1FFFFh 40000h 3FFFFh 18000h 17FFFh 30000h 2FFFFh 10000h 0FFFFh 20000h 1FFFFh 08000h 07FFFh 10000h 0FFFFh 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 00000h 00000h Byte-Wide Word-Wide 32K MAIN BLOCK 8K PARAMETER BLOCK 8K PARAMETER BLOCK 16K BOOT BLOCK 0FFFFh 08000h 07FFFh 06000h 05FFFh 04000h 03FFFh 00000h 07FFFh 04000h 03FFFh 03000h 02FFFh 02000h 01FFFh 00000h AI01731B 5/33 5 Page M29W800T, M29W800B INSTRUCTIONS AND COMMANDS The Command Interface latches commands writ- ten to the memory. Instructions are made up from one or more commands to perform Read Memory Array, Read Electronic Signature, Read Block Pro- tection, Program, Block Erase, Chip Erase, Erase Suspen d and Erase Resume. Commands are made of address and data sequences. The in- structions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the instruction. They are followed by either further write cycles to confirm the first command or execute the command immediately. Command se- quencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Instructions are initialised by two initial Coded cy- cles which unlock the Command Interface.In addi- tion, for Erase, instruction confirmation is again preceded by the two Coded cycles. Status Register Bits P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 and Erase Timer DQ3 bits. Any read attempt during Program or Erase com- mand execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked. See Tables 9 and 10. Data Polling Bit (DQ7). When Programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on DQ7. During Erase operation, it outputs a ’0’. After com- pletion of the operation, DQ7 will output the bit last programmed or a ’1’ after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be per- formed at the address being programmed or at an address within the block being erased. If all the blocks selected for erasure are protected,DQ7 will be set to ’0’ for about 100µs, and then return to the previous addressed memory data value. See Fig- ure 11 for the Data Polling flowchart and Figure 10 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from ’0’ to ’1’ at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an ad- dress within a block being erased must be pro- vided. For a Read Operation in Erase Suspend mode, DQ7 will output ’1’ if the read is attempted on a blockbeing erased and the data value on other blocks. During Program operation in Erase Sus- pend Mode, DQ7 will have the same behaviour as in the normal program execution outside of the suspend mode. Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary data.DQ6 will toggle following toggling of either G, or E when G is low. The operation is completed when two suc- cessive reads yield the same output data. The next read will output the bit last programmedor a ’1’ after erasing. The toggle bit DQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the blocks selected for erasure are pro- tected, DQ6 will toggle for about 100µs and then return back to Read. DQ6 will be set to ’1’ if a Read operationis attemptedon an Erase Suspendblock. When erase is suspended DQ6 will toggle during programming operations in a block different to the block in Erase Suspend. Either E or G toggling will cause DQ6 to toggle. See Figure 12 for Toggle Bit flowchart and Figure 13 for Toggle Bit waveforms. Table 7. Commands Hex Code Command 00h Invalid/Reserved 10h Chip Erase Confirm 20h Reserved 30h Block Erase Resume/Confirm 80h Set-up Erase 90h Read Electronic Signature/ Block Protection Status A0h Program B0h Erase Suspend F0h Read Array/Reset 11/33 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
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M29W800B	8 Mbit 1Mb x8 or 512Kb x16 / Boot Block Low Voltage Single Supply Flash Memory	ST Microelectronics
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