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PDF M29W400T-90M6TR Data sheet ( Hoja de datos )

Número de pieza M29W400T-90M6TR
Descripción 4 Mbit 512Kb x8 or 256Kb x16 / Boot Block Low Voltage Single Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M29W400T
M29W400B
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory
M29W400T and M29W400B are replaced
respectively by the M29W400BT and
M29W400BB
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 90ns
FAST PROGRAMMING TIME
– 10µs by Byte / 16µs by Word typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code, M29W400T: 00EEh
– Device Code, M29W400B: 00EFh
DESCRIPTION
The M29W400 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byteor Word-
by-Word basis using only a single 2.7V to 3.6V VCC
supply. For Program and Erase operations the
necessary high voltages are generated internally.
The device can also be programmed in standard
programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
NOT FOR NEW DESIGN
44
TSOP48 (N)
12 x 20 mm
1
SO44 (M)
BGA
FBGA48 (ZA)
8 x 6 solder balls
Figure 1. Logic Diagram
VCC
18
A0-A17
15
DQ0-DQ14
W DQ15A–1
M29W400T
E M29W400B BYTE
G RB
RP
VSS
AI02065
November 1999
This is information on a product still in productionbut not recommended for new designs.
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M29W400T-90M6TR pdf
M29W400T, M29W400B
Table 3A. M29W400T Block Address Table
Address Range (x8) Address Range (x16) A17 A16 A15 A14 A13 A12
00000h-0FFFFh
00000h-07FFFh 0 0 0 X X X
10000h-1FFFFh
08000h-0FFFFh
0 0 1 XXX
20000h-2FFFFh
10000h-17FFFh 0 1 0 X X X
30000h-3FFFFh
18000h-1FFFFh
0 1 1 XXX
40000h-4FFFFh
20000h-27FFFh 1 0 0 X X X
50000h-5FFFFh
28000h-2FFFFh
1 0 1 XXX
60000h-6FFFFh
30000h-37FFFh 1 1 0 X X X
70000h-77FFFh 38000h-3BFFFh 1 1 1 0 X X
78000h-79FFFh 3C000h-3CFFFh 1 1 1 1 0 0
7A000h-7BFFFh 3D000h-3DFFFh 1 1 1 1 0 1
7C000h-7FFFFh 3E000h-3FFFFh 1 1 1 1 1 X
Table 3B. M29W400B Block Address Table
Address Range (x8) Address Range (x16) A17 A16 A15 A14 A13 A12
00000h-03FFFh
00000h-01FFFh 0 0 0 0 0 X
04000h-05FFFh
02000h-02FFFh 0 0 0 0 1 0
06000h-07FFFh
03000h-03FFFh 0 0 0 0 1 1
08000h-0FFFFh
04000h-07FFFh 0 0 0 1 X X
10000h-1FFFFh
08000h-0FFFFh
0 0 1 XXX
20000h-2FFFFh
10000h-17FFFh 0 1 0 X X X
30000h-3FFFFh
18000h-1FFFFh
0 1 1 XXX
40000h-4FFFFh
20000h-27FFFh 1 0 0 X X X
50000h-5FFFFh
28000h-2FFFFh
1 0 1 XXX
60000h-6FFFFh
30000h-37FFFh 1 1 0 X X X
70000h-7FFFFh
38000h-3FFFFh
1 1 1 XXX
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
tection, Unprotection, Protection Verify, Unprotec-
tion Verify and Block Temporary Unprotection. See
Tables 4 and 5.
5/34

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M29W400T-90M6TR arduino
M29W400T, M29W400B
Table 9. Status Register Bits
DQ Name Logic Level
Definition
Note
7
Data
Polling
’1’
Erase Complete or erase
block in Erase Suspend
’0’ Erase On-going
Indicates the P/E.C. status, check during
Program or Erase, and on completion
DQ
Program Complete or data
of non erase block during
before checking bits DQ5 for Program or
Erase Success.
Erase Suspend
DQ Program On-going
’-1-0-1-0-1-0-1-’ Erase or Program On-going
6 Toggle Bit
DQ Program Complete
Erase Complete or Erase
’-1-1-1-1-1-1-1-’ Suspend on currently
addressed block
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
5 Error Bit
’1’ Program or Erase Error
This bit is set to ’1’ in the case of
Programming or Erase failure.
’0’ Program or Erase On-going
4 Reserved
3
Erase
Time Bit
P/E.C. Erase operation has started. Only
’1’ Erase Timeout Period Expired possible command entry is Erase
Suspend (ES).
’0’
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
Chip Erase, Erase or Erase
Suspend on the currently
’-1-0-1-0-1-0-1-’
addressed block.
Erase Error due to the
2 Toggle Bit
currently addressed block
(when DQ5 = ’1’).
Indicates the erase status and allows to
identify the erased block
Program on-going, Erase
1 on-going on another block or
Erase Complete
1 Reserved
DQ
Erase Suspend read on
non Erase Suspend block
0 Reserved
Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be per-
formed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to ’0’ for about 100µs, and then return to the
previous addressed memory data value. See Fig-
ure 11 for the Data Polling flowchart and Figure 10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
on a blockbeing erasedand the data value on other
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behaviour as
in the normal program execution outside of the
suspend mode.
11/34

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