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PDF SDA9488X Data sheet ( Hoja de datos )

Número de pieza SDA9488X
Descripción Cost-effective Picture-In-Picture ICs
Fabricantes ETC 
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PRELIMINARY DATA SHEET
SDA 9488X PIP IV Basic
SDA 9588X OCTOPUS
Cost-effective
Picture-In-Picture ICs
Edition Feb. 28, 2001
6251-561-1PD

1 page




SDA9488X pdf
SDA 9488X
SDA 9588X
Preliminary Data Sheet
Features
1 Features
• Single chip solution:
– AD-conversion for CVBS or Y/C or YUV1), multistandard color decoding, PLL for
synchronization of inset channel, decimation filtering, embedded memory, RGB-
matrix, DA-conversion, RGB/YUV switch, data-slicer and clock generation
integrated on chip
• Analog inputs:
– 3x CVBS or 1x CVBS and 1x Y/C or 1xYUV (SDA 9588X) alternatively
– Clamping of each input
– All ADCs with 8 bit amplitude resolution
– Automatic Gain Control (AGC) for Y and CVBS
• Inset Synchronization:
– Multiple time constants for reliable synchronization
– Automatic recognition of 625 lines / 525 lines standard
• Color Decoder:
– PAL-B/G, PAL-M, PAL-N(Argentina), PAL60, NTSC-M, NTSC4.4 and SECAM
– Adjustable color saturation
– Hue control for NTSC
– Automatic Chroma Control (-24 dB ... +6 dB)
– Automatic recognition of chroma standards: different search strategies selectable
– Single crystal for all standards
– IF-characteristic compensation filter
• Decimation:
– PIP sizes between 1/81 and 1/9 adjustable with steps of 2 lines and 4 pixel
– Resolution up to 216 luminance and 2x54 chrominance pixels per inset line
– Horizontal and vertical filtering dependent on picture size
• Display Features:
– 7 bit per pixel stored in memory
– Field and joint-line free frame mode display
– Display on VGA and SVGA screen (fH limited to 40kHz)
– 8 different read frequencies for 16:9 compatibility
– Line doubling mode for progressive scan applications
– Freeze picture
– Coarse positioning at 4 corners of the parent picture
– Fine positioning at steps of 4 pixels and 2 lines
• Output signal processing:
– 7 Bit DAC
– RGB or YUV switch: insertion of an external source without PIP processing
– Digital interpolation for anti-imaging
1) available with SDA 9588X only
Micronas
1-5

5 Page





SDA9488X arduino
SDA 9488X
SDA 9588X
Preliminary Data Sheet
System Description
The clamping pulse can be shifted in position (CLMPIST) and length (CLMPID) to adjust
to the specific application. The ADCs are driven by a 20.25 MHz free running crystal
clock which is not related to the incoming CVBS signal.
To avoid aliasing by subsampling the CVBS signal and the Y/C signals should be
bandlimited to 10MHz. In the same manner the U/V signal frequency spectrum (SDA
9588X) should not exceed 5 MHz. The digital filtering suppresses all frequencies above
the useable spectrum.
4.1.3
Automatic Gain Control
To accommodate to different CVBS input voltages an automatic gain control has been
implemented. The chip works correctly for input voltages in the range from 0.5 to 1.5Vpp.
For best signal-to-noise ratio, the maximum CVBS amplitude is recommended if
available. The AGC behavior can be chosen out of four possibilities (AGCMDE):
The sync height serves as reference for the gain control in the typical application. When
using overflow detection only, the gain is set to maximum and is reduced whenever an
overflow occurs. This procedure will be executed again when a channel change is
detected or the gain control is manually reset by AGCRES.
Automatic Gain Control Characteristic
2
1.5
1
0.5
0
0 2 4 6 8 10 12 14 16
AGCVAL
Figure 4-2 AGC characteristic
4.1.4
Signal Magnitudes
The nominal CVBS signal with 75% color has a magnitude of 1 Vpp. The upper headroom
is left to permit signals with 100% color resulting in 1.23 Vpp. The Y signal must always
contain the sync part. Its levels correspond to the CVBS levels except for the missing
color and burst. After A/D conversion the video part is clamped to its black value and is
amplified to 224 digital steps. The nominal signal levels ensure correct brightness and
saturation. The YUV signal levels conform to the ITU 601 recommendation.
Micronas
4-11

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