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PDF SDA9254-2 Data sheet ( Hoja de datos )

Número de pieza SDA9254-2
Descripción 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter
Fabricantes Siemens 
Logotipo Siemens Logotipo



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No Preview Available ! SDA9254-2 Hoja de datos, Descripción, Manual

2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM) with
On-chip Noise Reduction Filter
SDA 9254-2
Preliminary Data
CMOS IC
Features
q Stores a complete video field (4:1:1)
q On chip adaptive recursive noise reduction filter (4:1:1)
q 4 noise reduction classes selectable
q Special noise reduction mode for 4:2:2 applications
q 212 × 64 × 16 × 12-bit organization
q Triple port architecture
q One 16 × 12-bit input shift register
q Two 16 × 12-bit output shift registers
q Shift registers independently and simultaneously
accessible (one output shift register is used internally for
noise reduction filtering)
q Continuous data flow even at maximum speed
q 40-MHz shift rate - 0.96-Gbit/s total data rate
q All inputs and outputs TTL-compatible
q Tristate outputs
q Random access of groups of 16 × 12 bits for a wide range
of applications
q Refresh-free operation possible
q 5 V ± 10 % power supply
q 0 … 70 °C operating temperature range
q Low power dissipation: 700 mW active, 28 mW standby
q Suitable for all common TV standards
q Allows flicker and noise reduction simultaneously
with only one field memory
q Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
P-MQFP-64-1
Type
SDA 9254-2
Ordering Code
on request
Semiconductor Group
1
Package
P-MQFP-64-1
1998-01-16

1 page




SDA9254-2 pdf
SDA 9254-2
The following diagram shows the requested data format for 4:1:1 signals at the input
SDC0 … SDC11. The output data format at pins SQA0 … SQA11 corresponds to the input format.
BLN
13.5 MHz
SDC 4 ... 11
SDC 3
SDC 2
SDC 1
SDC 0
Y1 Y2 Y3 Y4 Y5 Y6
U1,7 U1,5 U1,3 U1,1 U2,7 U2,5
U1,6 U1,4 U1,2 U1,0 U2,6 U2,4
V1,7 V1,5 V1,3 V1,1 V2,7 V2,5
V1,6 V1,4 V1,2 V1,0 V2,6 V2,4
UED08600
Figure 4
Input Data Format (4:1:1)
Memory
The memory has a capacity of 2605056 bit. It is organized as 212 rows by 64 columns by 16 arrays
by 12 bit and allows the storage of the active part of a complete 4:1:1-TV field using a 13.5 MHz
sample rate. The memory is fabricated using the same CMOS technology used for 4-Mbit standard
dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 12-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 x 12-bit input
shift register C to an addressed location of the memory array and from the memory array to one of
the 16 x 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column address
(SAC) which contains the desired column address and an instruction code (mode bits) for transfer
and refresh.
Semiconductor Group
5
1998-01-16

5 Page





SDA9254-2 arduino
SDA 9254-2
Pin Configuration
(top view)
P-MQFP-64-1
Figure 6
SDC4
SDC5
SCA
SAR
SAC
SCAD
RE
V DD1
V SS1
RA
RB
WT
CLASS2
SCB
SDC6
SDC7
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49 32
50 31
51 30
52 29
53 28
54 27
55 26
56
57
SDA 9254-2
25
24
58 23
59 22
60 21
61 20
62 19
63 18
64 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SQA2
SQA3
V DD2
V SS2
SQA4
SQA5
OEA
V SS1
V DD1
OEDL0
SQA6
SQA7
V SS2
V DD2
SQA8
SQA9
UEP10382
Semiconductor Group
11
1998-01-16

11 Page







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