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PDF SDA9188-3X Data sheet ( Hoja de datos )
| Número de pieza | SDA9188-3X | |
| Descripción | Picture-in-Picture Processor with On-Chip PLL | |
| Fabricantes | Siemens | |
| Logotipo |  |
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Picture-in-Picture Processor with On-Chip PLL
SDA 9188-3X
Preliminary Data
MOS IC
Features
q On-chip PLL
q Full frame display for 50/60 Hz in order to increase the
vertical resolution and to suppress moving artifacts.
q Compatibility to the 16:9 display format by means of
independent setting of the vertical and horizontal
decimation factors and the width of the border frame
q Decimation of the Y, U, V data for pictures sizes 1/9
and 1/16 with 6 bits width of the input word without
rounding error
P-DSO-28-3
q Intermediate storage of the inset picture (on-chip-memory)
q RGB- or Y-, U-, V-signal generation
q 100% pin- and software compatible with SDA 9188X if external PLL is used
q Increased bandwith of analog outputs due to higher output currents
q New select function for multi-PIP feature
Type
SDA 9188-3X
Ordering Code
Q67100-H5142
Package
P-DSO-28-3 (350 mil) (SMD)
Functional Description
The SDA 9188-3X Picture-in-Picture (PIP) processor with on-chip PLL combines two asynchronous
picture sources so that a small moving picture (the inset picture) can be superimposed in a moving
picture of normal size (the parent picture).
The components of the video signal of the inset source have to be fed in a digitized form to the
SDA 9188-3X (figure 1). Amplitude resolution of the signal components is 6 bit at a sampling rate
of 13.5 MHz for the luminance signal and 3.375 MHz for the chrominance signals.
Semiconductor Group
1
08.93
1 page  
SDA 9188-3X
Block Diagram
Semiconductor Group
5
5 Page 
SDA 9188-3X
I2C BUS
Organization of I2C Bus Registers
SDA 9188-3X has the device address
00101110 = 2EH
Applying the supply voltage VDD produces a power-up reset. The bus lines SDA and SCL are
enabled. All bits in the registers except bit PL27 (D3 in Register 0) are set to 0. Bit PL27 is set to 1.
The I2C bus interface works as a slave receiver and only functions if the inset clock LL3I is available.
Write Operation
S 0010 1110 A
↑
0000 XXXX A
XXXX XXXX A
P
↑ → Ack
Wwrriittee
Start
↑
Stop
Chip address byte
Register address
Data word1
After writing a byte into any register, the register address is automatically incremented for the write
access to the next register.
The following table shows the functions that can be set on the I2C bus and define the data bytes. Not
used data bits have to be written with “0“ . Before PON = 1 all other bits have to be defined in
relation to the used hardware.
Function
CONTROL 0
CONTROL 1
CONTROL 2
CONTROL 3
CONTROL 4
CONTROL 5
CONTROL 6
CONTROL 7
CONTROL 8
CONTROL 9
SUB-
address
D7
D6
00 0 0
01 0 0
02 0 SD2
03 POS 1 POS 0
04
CON0
CON1
05 DECVER DECHOR
06 FRAME STATI
07 AMSEC STATP
08 0 0
09 0 PLLTC
D5
STILL
0
SD1
RDH 5
CON2
FRWV
VSIIS
VSPIS
0
SOS
D4 D3 D2 D1 D0
SIZE
PL27
NINT
OUT
PON
FRY
COL2
COL1
COL0
FRON
SD0 RDV 3 RDV 2 RDV 1 RDV 0
RDH 4 RDH 3 RDH 2 RDH 1 RDH 0
CON3
0
SOP PLLOFF HSP5
FRWH PMOD1 PMOD0 IMOD1 IMOD0
VSIDEL4 VSIDEL3 VSIDEL2 VSIDEL1 VSIDEL0
VSPDEL4 VSPDEL3 VSPDEL2 VSPDEL1 VSPDEL0
FRYEN FRY5
FRY4
FRY3
FRY2
VCOSEL3 VCOSEL2 VCOSEL1 VCOSEL0
0
Table 6: I2C Bus Register
The bits are numbered in the reverse order to the data stream of the I2C bus.
If the control software addresses the internal register number 8 or 9 there is no longer any software
compatibility to the devices SDA 9088-2 and SDA 9089X. This is caused by the fact that in these
devices register 0 and 1 can also be accessed via the subaddress 08 and 09.
Semiconductor Group
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SDA9188-3X.PDF ] | |
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