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PDF SDA2516 Data sheet ( Hoja de datos )
| Número de pieza | SDA2516 | |
| Descripción | Nonvolatile Memory 1-Kbit E2PROM | |
| Fabricantes | Siemens | |
| Logotipo |  |
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Nonvolatile Memory 1-Kbit E2PROM
Preliminary Data
SDA 2516-5
MOS IC
Features
q Word-organized reprogrammable nonvolatile memory
in n-channel floating-gate technology (E2PROM)
q 128 × 8-bit organization
q Supply voltage 5 V
q Serial 2-line bus for data input and output (I2C Bus)
q Reprogramming mode, 10 ms erase/write cycle
q Reprogramming by means of on-chip control (without
external control)
q Check for end of programming process
q Data retention > 10 years
q More than 104 reprogramming cycles per address
q Compatible with SDA 2516. Exception:
Conditions for total erase and current consumption ICC.
Type
SDA 2516-5
Ordering Code
Q67100-H5092
P-DIP-8-1
Package
P-DIP-8-1
Circuit Description
I2C Bus Interface
The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external
pull-up resistor to VCC (open drain output stage).
The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains
"1", information changes on the data bus indicate the start or the end of data transfer between two
components.
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" a stop
condition. During a data transfer the information on the data bus will only change while the clock line
SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an I2C Bus system, the memory component can operate as a receiver and as a
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is
always transmitted in byte-organized form. Between the trailing edge of the eighth clock pulse and
Semiconductor Group
5
07.94
1 page  
SDA 2516-5
Block Diagram
Semiconductor Group
9
5 Page 
SDA 2516-5
Figure 3
Programming
Control word input
ST CS/E As
WA
As
DE
As
SP
(the reprogramming starts after
this stop condition)
Check for program end by ST CS/A As
1. when As = 1 programming is not finished
2. when As = 0 programming is finished
Program interruption by
ST CS/E As
Figure 4
Read
Control word input read
a) complete (with word address input)
ST CS/E As WA As ST CS/A As DA Am DA Am SP
n bytes
Last byte
Automatic incrementation
of the word address
b) shortened:
Bit 0 … 7 the last adapted word
address keep unchanged
ST CS/A As DA Am DA Am SP
n bytes
Last byte
Autoincrement
before stop condition
Am = 0
Am = 1
Semiconductor Group
15
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet SDA2516.PDF ] | |
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