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PDF 74VHC161 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC161 | |
| Descripción | 4-Bit Binary Counter with Asynchronous Clear | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1993
Revised April 1999
74VHC161
4-Bit Binary Counter with Asynchronous Clear
General Description
The VHC161 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC161 is a high-speed synchronous modulo-
16 binary counter. This device is synchronously presettable
for application in programmable dividers and have two
types of Count Enable inputs plus a Terminal Count output
for versatility in forming synchronous multistage counters.
The VHC161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW. An
input protection circuit insures that 0V to 7V can be applied
to the input pins without regard to the supply voltage. This
device can be used to interface 5V to 3V systems and two
supply systems such as battery backup. This circuit pre-
vents device destruction due to mismatched supply and
input voltages.
Features
s High Speed:
fMAX = 185 MHz (typ) at TA = 25°C
s Synchronous counting and loading
s High-speed synchronous expansion
s Low power dissipation:
ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection provided on all inputs
s Low noise: VOLP = 0.8V (max)
s Pin and function compatible with 74HC161
Ordering Code:
Order Number Package Number
Package Description
74VHC161M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC161SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC161MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC161N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS011635.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = 25°C
TA = −40° to +85°C
Units
Conditions
(V) Min Typ Max Min Max
tPLH Propagation Delay
tPHL Time (CP–Qn)
tPLH Propagation Delay
tPHL Time (CP–TC, Count)
tPLH Propagation Delay
tPHL Time (CP–TC, Load)
tPLH Propagation Delay
tPHL Time (CET–TC)
tPHL Propagation Delay
Time (MR –Qn)
tPHL Propagation Delay
Time (MR –TC)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
8.3
12.8
1.0
15.0
ns CL = 15 pF
10.8
16.3
1.0
18.5
CL = 50 pF
4.9 8.1 1.0 9.5 ns CL = 15 pF
6.4 10.1 1.0 11.5
CL = 50 pF
8.7
13.6
1.0
16.0
ns CL = 15 pF
11.2 17.1 1.0 19.5
CL = 50 pF
4.9 8.1 1.0 9.5 ns CL = 15 pF
6.4 10.1 1.0 11.5
CL = 50 pF
11.0 17.2
1.0
20.0
ns CL = 15 pF
13.5
20.7
1.0
23.5
CL = 50 pF
6.2
10.3
1.0
12.0
ns CL = 15 pF
7.7 12.3 1.0 14.0
CL = 50 pF
7.5
12.3
1.0
14.5
ns CL = 15 pF
10.5
15.8
1.0
18.0
CL = 50 pF
4.9 8.1 1.0 9.5 ns CL = 15 pF
6.4 10.1 1.0 11.5
CL = 50 pF
8.9
13.6
1.0
16.0
ns CL = 15 pF
11.2 17.1 1.0 19.5
CL = 50 pF
5.5
9.0
1.0
10.5
ns CL = 15 pF
7.0 11.0 1.0 12.5
CL = 50 pF
8.4
13.2
1.0
15.5
ns CL = 15 pF
10.9
16.7
1.0
19.0
CL = 50 pF
fMAX
Maximum Clock
Frequency
CIN Input Capacitance
CPD Power Dissipation
Capacitance
5.0 ± 0.5
5.0
8.6
1.0
10.0
ns CL = 15 pF
6.5 10.6 1.0 12.0
CL = 50 pF
3.3 ± 0.3
80
55
130
85
70 MHz CL = 15 pF
50 CL = 50 pF
5.0 ± 0.5
135
95
185
125
115 MHz CL = 15 pF
85 CL = 50 pF
4 10
10 pF VCC = Open
23 pF (Note 4)
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fIN + ICC.
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ∆ICC which is obtained from the following formula:
CQ0–CQ3 and CTC are the capacitances at Q0–Q3 and TC, respectively. FCP is the input frequency of the CP.
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