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PDF 74VHC138 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC138 | |
| Descripción | 3 TO 8 LINE DECODER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74VHC138
3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED: tPD = 5.7ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
)s POWER DOWN PROTECTION ON INPUTS
t(ss SYMMETRICAL OUTPUT IMPEDANCE:
c|IOH| = IOL = 8 mA (MIN)
us BALANCED PROPAGATION DELAYS:
dtPLH ≅ tPHL
ros OPERATING VOLTAGE RANGE:
PVCC(OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
te74 SERIES 138
les IMPROVED LATCH-UP IMMUNITY
bsoDESCRIPTION
The 74VHC138 is an advanced high-speed
- OCMOS 3 TO 8 LINE DECODER (INVERTING)
)fabricated with sub-micron silicon gate and
t(sdouble-layer metal wiring C2MOS technology.
If the device is enabled, 3 binary select (A, B, and
cC) determine which one of the outputs will go low.
uIf enable input G1 is held low or either G2A or G2B
rodis held high, the decoding function is inhibited and
all the 8 outputs go to high.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC138MTR
74VHC138TTR
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Obsolete PFigure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 4
1/12
1 page  
74VHC138
Table 8: Capacitive Characteristics
Test Condition
Value
Symbol
Parameter
TA = 25°C
-40 to 85°C -55 to 125°C Unit
CIN Input Capacitance
CPD Power Dissipation
Capacitance
(note 1)
Min. Typ. Max. Min. Max. Min. Max.
6 10 10 10 pF
34 pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
)Figure 4: Test Circuit
uct(s) - Obsolete Product(sCL =15/50pF or equivalent (includes jig and probe capacitance)
dRT = ZOUT of pulse generator (typically 50Ω)
Obsolete ProFigure 5: Waveform - Propagation Delays For Inverting Outputs (f=1MHz; 50% duty cycle)
5/12
5 Page 
Table 9: Revision History
Date
12-Nov-2004
Revision
4
Description of Changes
Order Codes Revision - pag. 1.
74VHC138
Obsolete Product(s) - Obsolete Product(s)
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 74VHC138.PDF ] | |
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