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PDF 74VHC112 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC112 | |
| Descripción | Dual J-K Flip-Flops with Preset and Clear | |
| Fabricantes | Fairchild Semiconductor | |
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74VHC112
Dual J-K Flip-Flops with Preset and Clear
May 2007
tm
Features
■ High speed: fMAX = 200MHz (Typ.) at VCC = 5.0V
■ Low power dissipation: ICC = 2µA (Max.) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (Min.)
■ Power down protection is provided on all inputs
■ Pin and function compatible with 74HC112
General Description
The VHC112 is an advanced high speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The VHC112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous
state changes are initiated by the falling edge of the
clock. Triggering occurs at a voltage level of the clock
and is not directly related to transition time. The J and K
inputs can change when the clock is in either state with-
out affecting the flip-flop, provided that they are in the
desired state during the recommended setup and hold
times relative to the falling edge of the clock. The LOW
signal on PR or CLR prevents clocking and forces Q and
Q HIGH, respectively. Simultaneous LOW signals on PR
and CLR force both Q and Q HIGH.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Order Number
74VHC112M
74VHC112SJ
74VHC112MTC
Package
Number
M16A
M16D
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
©1995 Fairchild Semiconductor Corporation
74VHC112 Rev. 1.2
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
fMAX
Parameter
Maximum Clock
Frequency
tPLH, tPHL Propagation Delay Time
(CP to Qn or Qn)
tPLH, tPHL Propagation Delay Time
(PR or CLR to Qn or Qn)
CIN Input Capacitance
CPD Power Dissipation
Capacitance
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Conditions
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
VCC = Open
(2)
TA = 25°C
Min. Typ. Max.
110 150
90 120
150 200
120 185
8.5 11.0
10.0 15.0
5.1 7.3
6.3 10.5
6.7 10.2
9.7 13.5
4.6 6.7
6.4 9.5
4 10
18
TA = –40°C
to +85°C
Min. Max. Units
100 MHz
80
135 MHz
110
1.0 13.4 ns
1.0 16.5
1.0 8.8 ns
1.0 12.0
1.0 11.7 ns
1.0 15.0
1.0 8.0 ns
1.0 11.0
10 pF
pF
Note:
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
ICC (opr.) = CPD • VCC • fIN + ICC / 4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated
by the following equation: CPD (total) = 30 + 14 • n
AC Operating Requirements
Symbol
tW
Parameter
Minimum Pulse Width
(CP or CLR or PR)
tS
tH
tREC
Minimum Setup Time
(Jn or Kn to CPn)
Minimum Hold Time
(Jn or Kn to CPn)
Minimum Recovery Time
(CLR or PR to CP)
Note:
3. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V.
VCC (V)(3)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = 25°C
TA = –40°C to +85°C
Typ.
Guaranteed Minimum
5.0 5.0
5.0 5.0
5.0 5.0
4.0 4.0
1.0 1.0
1.0 1.0
6.0 6.0
5.0 5.0
Units
ns
ns
ns
ns
©1995 Fairchild Semiconductor Corporation
74VHC112 Rev. 1.2
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74VHC112.PDF ] | |
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