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PDF M48Z2M1Y Data sheet ( Hoja de datos )

Número de pieza M48Z2M1Y
Descripción 16 Mbit (2 Mb x 8) ZEROPOWER SRAM
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M48Z2M1Y
M48Z2M1V
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
Integrated, ultra low power SRAM, power-fail
control circuit, and batteries
Conventional SRAM operation; unlimited
)WRITE cycles
t(s10 years of data retention in the absence of
cpower
duAutomatic power-fail chip deselect and WRITE
roprotection
PWRITE protect voltages
te(VPFD = power-fail deselect voltage):
le– M48Z2M1Y: VCC = 4.5 to 5.5 V;
4.2 V VPFD 4.5 V
so– M48Z2M1V: VCC = 3.0 to 3.6 V;
b2.8 V VPFD 3.0 V
OBatteries are internally isolated until power is
-applied
t(s)Pin and function compatible with JEDEC
standard 2 Mb x 8 SRAMs
ucRoHS compliant
Obsolete Prod– Lead-free second level interconnect
36
1
PLDIP36 module
June 2011
Doc ID 5135 Rev 6
This is information on a product still in production but not recommended for new designs.
1/20
www.st.com
1

1 page




M48Z2M1Y pdf
M48Z2M1Y, M48Z2M1V
1 Description
Description
The M48Z2M1Y/V ZEROPOWER® RAM is a non-volatile 16,777,216-bit, static RAM
organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries,
CMOS SRAMs and a control circuit in a plastic 36-pin DIP, long module.
The ZEROPOWER RAM replaces industry standard SRAMs. It provides the non-volatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
WRITEs that can be performed.
Figure 1. Logic diagram
VCC
t(s)21
A0-A20
8
DQ0-DQ7
ducW M48Z2M1Y
M48Z2M1V
roE
PG
oleteVSS
bsTable 1. Signal names
- OA0-A20
Address inputs
t(s)DQ0-DQ7
Data inputs / outputs
cE Chip enable
duG Output enable
roW WRITE enable
PVCC Supply voltage
lete VSS Ground
Obso NC Not connected internally
AI02048
Doc ID 5135 Rev 6
5/20

5 Page





M48Z2M1Y arduino
M48Z2M1Y, M48Z2M1V
Operation modes
2.4 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
)1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
t(smount.
ucFigure 8. Supply voltage protection
ProdVCC
VCC
lete0.1µF
DEVICE
Obsolete Product(s) - ObsoVSS
AI02169
Doc ID 5135 Rev 6
11/20

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