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PDF M48Z129V Data sheet ( Hoja de datos )
| Número de pieza | M48Z129V | |
| Descripción | 1 Mbit (128 Kb x 8) ZEROPOWER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48Z129V
3.3 V, 1 Mbit (128 Kb x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ Conventional SRAM operation; unlimited
)WRITE cycles
t(s■ 10 years of data retention in the absence of
cpower
du■ Microprocessor power-on reset (reset valid
roeven during battery backup mode)
P■ Battery low pin - provides warning of battery
end-of-life
lete■ Automatic power-fail chip deselect and WRITE
protection
so■ WRITE protect voltages
Ob– VCC = 3.0 to 3.6 V; 2.7 V ≤ VPFD ≤ 3.0 V
-(VPFD = power-fail deselect voltage)
)■ Self-contained battery in the CAPHAT™ DIP
t(spackage
c■ Pin and function compatible with JEDEC
ustandard 128 K x 8 SRAMs
rod■ RoHS compliant
Obsolete P– Lead-free second level interconnect
32
1
PMDIP32 module
September 2011
Doc ID 5716 Rev 8
This is information on a product still in production but not recommended for new designs.
1/20
www.st.com
1
1 page  
M48Z129V
1 Description
Description
The M48Z129V ZEROPOWER® SRAM is a 1,048,576 bit non-volatile static RAM organized
as 131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM
and a control circuit in a plastic 32-pin DIP module. The M48Z129V directly replaces
industry standard 128 K x 8 SRAM. It also provides the non-volatility of FLASH without any
requirement for special WRITE timing or limitations on the number of WRITEs that can be
performed.
Figure 1. Logic diagram
VCC
t(s)17
cA0-A16
duW
M48Z129V
roE
PG
8
DQ0-DQ7
RST
BL
soleteVSS
- ObTable 1. Signal names
)A0-A16
Address inputs
t(sDQ0-DQ7
Data inputs / outputs
ucE Chip enable
rodG Output enable
PW WRITE enable
te RST
Reset output (open drain)
le BL Battery low output (open drain)
bso VCC Supply voltage
O VSS Ground
AI02309
Doc ID 5716 Rev 8
5/20
5 Page 
M48Z129V
Operation modes
2.4 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
)1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
t(smount.
ucFigure 8. Supply voltage protection
ProdVCC
VCC
lete0.1µF
DEVICE
Obsolete Product(s) - ObsoVSS
AI02169
Doc ID 5716 Rev 8
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet M48Z129V.PDF ] | |
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