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PDF M48Z128Y Data sheet ( Hoja de datos )
| Número de pieza | M48Z128Y | |
| Descripción | 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48Z128
M48Z128Y
5.0 V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ Conventional SRAM operation; unlimited
)WRITE cycles
t(s■ 10 years of data retention in the absence of
cpower
du■ Battery internally isolated until power is first
roapplied
P■ Automatic power-fail chip deselect and WRITE
protection
lete■ WRITE protect voltages:
o(VPFD = power-fail deselect voltage)
s– M48Z128: VCC = 4.75 to 5.5 V;
b4.5 V ≤ VPFD ≤ 4.75 V
O– M48Z128Y: VCC = 4.5 to 5.5 V;
) -4.2 V ≤ VPFD ≤ 4.5 V
t(s■ Pin and function compatible with JEDEC
standard 128 K x 8 SRAMs
uc■ RoHS compliant
Obsolete Prod– Lead-free second level interconnect
32
1
PMDIP32 module
September 2011
Doc ID 2426 Rev 6
This is information on a product still in production but not recommended for new designs.
1/20
www.st.com
1
1 page  
M48Z128, M48Z128Y
1 Description
Description
The M48Z128/Y ZEROPOWER® RAM is a 128 Kbit x 8 non-volatile static RAM organized
as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM
and a control circuit in a plastic, 32-pin DIP module to provide a highly integrated battery-
backed memory solution.
The M48Z128/Y is a non-volatile pin and function equivalent to any JEDEC standard
128 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP
module houses the M48Z128/Y silicon with a long-life lithium button cell in a single package.
ct(s)Figure 1. Logic diagram
VCC
rodu17
PA0-A16
8
DQ0-DQ7
leteW M48Z128
oM48Z128Y
sE
ObG
Obsolete Product(s) -Table 1.
Signal names
A0-A16
DQ0-DQ7
E
G
W
VSS
Address inputs
Data inputs / outputs
Chip enable input
Output enable input
WRITE enable input
AI01194
VCC Supply voltage
VSS Ground
NC Not connected internally
Doc ID 2426 Rev 6
5/20
5 Page 
M48Z128, M48Z128Y
Operating modes
2.4 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see Figure 8)
is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, ST recommends connecting a schottky
diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817
)is recommended for through hole and MBRS120T3 is recommended for surface-mount).
t(sFigure 8. Supply voltage protection
roducVCC
VCC
lete P0.1µF
DEVICE
Obsolete Product(s) - ObsoVSS
AI02169
Doc ID 2426 Rev 6
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet M48Z128Y.PDF ] | |
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| M48Z128Y | 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM | ST Microelectronics |
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