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PDF M48Z128V Data sheet ( Hoja de datos )
| Número de pieza | M48Z128V | |
| Descripción | 5.0V OR 3.3V / 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48Z128
M48Z128Y, M48Z128V*
5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM
FEATURES SUMMARY
s INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY
s CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s 10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
s BATTERY INTERNALLY ISOLATED UNTIL
POWER IS FIRST APPLIED
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage)
– M48Z128: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V
– M48Z128Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
– M48Z128V: VCC = 3.0 to 3.6V
2.8V ≤ VPFD ≤ 3.0V
s SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP WHICH
CONTAINS THE BATTERY
s SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE
s PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
s EQUIVALENT SURFACE-MOUNT (SMT)
SOLUTION REQUIRES A 28-PIN M40Z300/W
and A STAND-ALONE 128K x8 LPSRAM
(SNAPHAT® Top to be ordered separately)
Figure 1. 32-pin PMDIP Module
32
1
PMDIP32 (PM)
Module
* Contact Local Sales Office
October 2003
Rev. 3.4
1/21
1 page  
M48Z128, M48Z128Y, M48Z128V*
Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution
SNAPHAT
BATTERY(3)
THS(1,2) VOUT
M40Z300/W
E E1CON
E2CON
E3CON
E4CON
A
RST
B
BL
VSS
VCC
E2
1Mb LPSRAM
E
DQ0-DQ7
A0-A16
W
VSS
AI03625
Note: For pin connections, see individual data sheet for M48Z300/300W at www.st.com.
1. Connect THS pin to VOUT if 4.2V ≤ VPFD ≤ 4.5V (M48Z128Y) or connect THS pin to VSS if 4.5V ≤ VPFD ≤ 4.75V (M48Z128).
2. Connect THS pin to VSS if 2.8V ≤ VPFD ≤ 3.0V (M48Z128V).
3. SNAPHAT® Top ordered separately.
Table 2. Equivalent Surface-Mount (SMT) Solution
NVRAM
LPSRAM
SUPERVISOR
M48Z128
5V 1Mb LPSRAM
M40Z300
M48Z128Y
5V 1Mb LPSRAM
M40Z300
M48Z128V
3V 1Mb LPSRAM
M40Z300W
Note: 1. Connection of Threshold Select Pin (Pin 13) of SUPERVISOR (M40Z300/300W).
THS Pin(1)
VSS
VOUT
VSS
5/21
5 Page 
M48Z128, M48Z128Y, M48Z128V*
WRITE Mode
The M48Z128/Y/V is in the WRITE Mode whenev-
er W and E are active. The start of a WRITE is ref-
erenced from the latter occurring falling edge of W
or E. A WRITE is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of
tEHAX from E or tWHAX from W prior to the initiation
of another READ or WRITE cycle. Data-in must be
valid tDVWH prior to the end of WRITE and remain
valid for tWHDX or tEHDX afterward. G should be
kept high during WRITE cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on E and G, a low on W will disable
the outputs tWLQZ after W falls.
Figure 9. WRITE Enable Controlled, WRITE AC Waveforms
A0-A16
E
tAVEL
tAVWL
tAVAV
VALID
tAVWH
tWLWH
W
DQ0-DQ7
tWLQZ
tWHDX
DATA INPUT
tDVWH
Note: Output Enable (G) = High.
tWHAX
tWHQX
AI01198
Figure 10. Chip Enable Controlled, WRITE AC Waveforms
A0-A16
E
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tEHAX
W
tEHDX
DQ0-DQ7
DATA INPUT
Note: Output Enable (G) = High.
tDVEH
AI01199
11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet M48Z128V.PDF ] | |
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