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PDF M48T59 Data sheet ( Hoja de datos )
| Número de pieza | M48T59 | |
| Descripción | 64 Kbit 8Kb x8 TIMEKEEPER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48T59
M48T59Y/M48T59V
64 Kbit (8Kb x8) TIMEKEEPER® SRAM
PRELIMINARY DATA
s INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
s FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T59: 4.5V ≤ VPFD ≤ 4.75V
– M48T59Y: 4.2V ≤ VPFD ≤ 4.5V
– M48T59V: 2.7V ≤ VPFD ≤ 3.0V
s SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
s PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT® TOP
(to be Ordered Separately)
s SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
s MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
s PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACK-UP MODE
s BATTERY LOW FLAG
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
IRQ/FT
Interrupt / Frequency Test
Output (Open Drain)
RST
Power Fail Reset Output
(Open Drain)
E Chip Enable
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
SNAPHAT (SH)
Battery/Crytstal
28
1
SOH28 (MH)
28
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
Figure 1. Logic Diagram
VCC
13
A0-A12
8
DQ0-DQ7
W M48T59
M48T59Y
E
M48T59V
IRQ/FT
G RST
VSS
AI01380E
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/21
1 page  
M48T59, M48T59Y, M48T59V
Table 8. Power Down/Up AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C)
Symbol
Parameter
Min Max Unit
tPD E or W at VIH before Power Down
0 µs
tF (1)
VPFD (max) to VPFD (min) VCC Fall Time
300 µs
tFB (2)
VPFD (min) to VSS VCC Fall Time
M48T59/Y
M48T59V
10
150
µs
µs
tR VPFD (min) to VPFD (max) VCC Rise Time
10 µs
tRB VSS to VPFD (min) VCC Rise Time
1 µs
tREC (3) VPFD (max) to RST High
40 200 ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
es VPFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
3. tREC (min) = 20ms for industrial temperature grade 6 device.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tPD
tF
tFB
RST
INPUTS
RECOGNIZED
OUTPUTS
VALID
(PER CONTROL INPUT)
tR
tRB
tDR
tREC
DON'T CARE
HIGH-Z
RECOGNIZED
VALID
(PER CONTROL INPUT)
AI03258
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is "M4T28-BR12SH" or “M4T32-BR12SH”.
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T59/59Y/59V are integrated on one silicon
chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format (except
for the century). Corrections for 28, 29 (leap year),
30, and 31 day months are made automatically.
Byte 1FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
5/21
5 Page 
M48T59, M48T59Y, M48T59V
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 12). Resetting the WRITE bit to
a ’0’ then transfers the values of all time registers
(1FF9h-1FFFh) to the actual TIMEKEEPER
counters and allows normal operation to resume.
After the WRITE bit is reset, the next clock update
will occur within approximately one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ‘0’.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T59/59Y/59V in
the DIP package, is shipped from
STMicroelectronics with the STOP bit set to a '1'.
When reset to a '0', the M48T59/59Y/59V oscilla-
tor starts within one second.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT), the STOP bit (ST) or the CENTURY EN-
ABLE bit (CEB).
Calibrating the Clock
The M48T59/59Y/59V is driven by a quartz con-
trolled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed
35 ppm (parts per million) oscillator frequency er-
ror at 25°C, which equates to about ±1.53 minutes
per month. With the calibration bits properly set,
the accuracy of each M48T59/59Y/59V improves
to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T59/59Y/59V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five bit Calibration byte found in the
Control Register. Adding counts speeds the clock
up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (1FF8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
Figure 10. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
–40 –30 –20 –10
0
∆F
F
= -0.038
ppm
C2
(T
-
T0)2
±
10%
T0 = 25 °C
10 20 30 40 50 60 70 80
Temperature °C
AI00999
11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet M48T59.PDF ] | |
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