|
|
PDF M48T513Y Data sheet ( Hoja de datos )
| Número de pieza | M48T513Y | |
| Descripción | 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M48T513Y (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
|
No Preview Available !
M48T513Y
M48T513V
3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPER® SRAM
s INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY, and CRYSTAL
s YEAR 2000 COMPLIANT
s BCD CODED CENTURY, YEAR, MONTH,
DAY, DATE, HOURS, MINUTES, and
SECONDS
s BATTERY LOW WARNING FLAG
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s TWO WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage)
– M48T513Y: 4.2V ≤ VPFD ≤ 4.5V
– M48T513V: 2.7V ≤ VPFD ≤ 3.0V
s CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s SOFTWARE CONTROLLED CLOCK
CALIBRATION for HIGH ACCURACY
APPLICATIONS
s 10 YEARS of DATA RETENTION and CLOCK
OPERATION in the ABSENCE of POWER
s SELF CONTAINED BATTERY and CRYSTAL
in DIP PACKAGE
s MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
s PROGRAMMABLE ALARM OUTPUT ACTIVE
in BATTERY BACK-UP MODE
s SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 44-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
s SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY and CRYSTAL
s SNAPHAT® HOUSING (BATTERY/CRYSTAL)
IS REPLACEABLE
32
1
PMDIP32 (PM)
Module
SNAPHAT (SH)
Battery
32
1
TSOP II 32
(10 x 20mm)
SOH44
Surface Mount Chip Set Solution (CS)
Figure 1. Logic Diagram
VCC
19
A0-A18
8
DQ0-DQ7
W
E
G
WDI
RSTIN
M48T513Y
M48T513V
RST
IRQ/FT
VSS
AI02308
June 2000
1/23
1 page  
M48T513Y, M48T513V
Table 3. Operating Modes (1)
Mod e
VCC
EG
Deselect
VIH X
Write
Read
4.5V to 5.5V
or
3.0V to 3.6V
VIL X
VIL VIL
Read
VIL VIH
Deselect
VSO to VPFD (min) (2)
XX
Deselect
≤ VSO (2)
XX
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
W DQ0-DQ7
X High Z
VIL DIN
VIH DOUT
VIH High Z
X High Z
Power
Standby
Active
Active
Active
CMOS Standby
X High Z Battery Back-up Mode
DATA RETENTION MODE
With valid VCC applied, the M48T513Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally deselect, write protecting itself when VCC
falls between VPFD (max), VPFD (min) window. All
outputs become high impedance and all inputs are
treated as ”don’t care”.
Note: A power failure during a write cycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD (min), the memory will be
in a write protected state, provided the VCC fall
time is not less than tF. The M48T513Y/V may re-
spond to transient noise spikes on VCC that cross
into the deselect window during the time the de-
vice is sampling VCC. Therefore, decoupling of the
power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T513Y/V for
an accumulated period of at least 10 years at room
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Deselect continues for
tREC after VCC reaches VPFD (max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.
TIMEKEEPER REGISTERS
The M48T513Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
Table 4. AC Measurement Conditions
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Figure 5. AC Testing Load Circuit
DEVICE
UNDER
TEST
650Ω
CL = 100pF
1.75V
CL includes JIG capacitance
Note: Excluding open drain output pins.
AI01803C
referred to as BiPORT™ TIMEKEEPER cells).
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD.
5/23
5 Page 
M48T513Y, M48T513V
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
A0-A16
E
G
DQ0-DQ7
tAVAV
VALID
tAVQV
tELQV
tELQX
tGLQV
tGLQX
tAXQX
tEHQZ
tGHQZ
DATA OUT
AI01197
Figure 9. Write Enable Controlled, Write AC Waveforms
A0-A16
E
W
DQ0-DQ7
tAVEL
tAVAV
VALID
tAVWH
tWHAX
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI02382
11/23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet M48T513Y.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M48T513V | 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM | ST Microelectronics |
| M48T513Y | 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM | ST Microelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |