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PDF M48T35Y Data sheet ( Hoja de datos )
| Número de pieza | M48T35Y | |
| Descripción | 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM | |
| Fabricantes | ST Microelectronics | |
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M48T35
M48T35Y
5 V, 256 Kbit (32 Kb x 8) TIMEKEEPER® SRAM
Features
■ Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit and battery
■ BYTEWIDE™ RAM-like clock access
■ BCD coded year, month, day, date, hours,
minutes, and seconds
■ Frequency test output for real-time clock
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
VPFD = power-fail deselect voltage):
– M48T35: VCC = 4.75 to 5.5 V;
4.5 V ≤ VPFD ≤ 4.75 V
– M48T35Y: VCC = 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
■ Self-contained battery and crystal in the
CAPHAT™ DIP package
■ SOIC package provides direct connection for a
SNAPHAT® housing containing the battery and
crystal
■ SNAPHAT® housing (battery and crystal) is
replaceable
■ Pin and function compatible with JEDEC
standard 32 Kb x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
28
1
PCDIP28
Battery/crystal
CAPHAT™
SNAPHAT®
Battery/crystal
28
1
SOH28
June 2011
Doc ID 2611 Rev 10
1/28
www.st.com
1
1 page  
M48T35, M48T35Y
1 Description
Description
The M48T35/Y TIMEKEEPER® RAM is a 32 Kb x 8 non-volatile static RAM and real-time
clock. The monolithic chip is available in two special packages to provide a highly integrated
battery-backed memory and real-time clock solution.
The M48T35/Y is a non-volatile pin and function equivalent to any JEDEC standard
32 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the M48T35/Y silicon with a quartz crystal and a
long life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT® housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and crystal damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in
plastic anti-static tubes or in tape & reel form.
For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28-
BR12SH”.
Figure 1. Logic diagram
VCC
15
A0-A14
8
DQ0-DQ7
W M48T35
M48T35Y
E
G
VSS
AI01620B
Doc ID 2611 Rev 10
5/28
5 Page 
M48T35, M48T35Y
Operation modes
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48T35/Y
Min Max
Unit
tAVAV WRITE cycle time
70 ns
tAVWL
tAVEL
tWLWH
tELEH
tWHAX
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
0
0
50
55
0
ns
ns
ns
ns
ns
tEHAX Chip enable high to address transition
0
ns
tDVWH
tDVEH
tWHDX
tEHDX
tWLQZ(2)(3)
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
30 ns
30 ns
5 ns
5 ns
25 ns
tAVWH Address valid to WRITE enable high
tAVEH Address valid to chip enable high
tWHQX(2)(3) WRITE enable high to output transition
60
60
5
ns
ns
ns
1. Valid for ambient operating temperature: TA = 0 to 70 or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Note:
Data retention mode
With valid VCC applied, the M48T35/Y operates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care” (see Figure 12 on
page 19, Table 10, and Table 11 on page 20).
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T35/Y may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T35/Y for an accumulated period of at least 7 years when VCC is less than VSO. As
system power returns and VCC rises above VSO, the battery is disconnected, and the power
supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min)
plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent
WRITE cycles prior to processor stabilization. Normal RAM operation can resume trec after
VCC exceeds VPFD (max).
For more information on battery storage life refer to the application note AN1012.
Doc ID 2611 Rev 10
11/28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet M48T35Y.PDF ] | |
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