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PDF M48T35AY Data sheet ( Hoja de datos )

Número de pieza M48T35AY
Descripción 256 Kbit 32Kb x8 TIMEKEEPER SRAM
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M48T35AY
M48T35AV
256 Kbit (32Kb x8) TIMEKEEPER® SRAM
s INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
s BYTEWIDE™ RAM-LIKE CLOCK ACCESS
s BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
s BATTERY LOW FLAG (BOK)
s FREQUENCY TEST OUTPUT for REAL TIME
CLOCK
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T35AY: 4.2V VPFD 4.5V
– M48T35AV: 2.7V VPFD 3.0V
s SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
s SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT HOUSING
CONTAINING the BATTERY and CRYSTAL
s SNAPHAT® HOUSING (BATTERY and
CRYSTAL) is REPLACEABLE
s PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32Kb x8 SRAMs
DESCRIPTION
The M48T35AY/35AV TIMEKEEPER® RAM is a
32Kb x8 non-volatile static RAM and real time
clock. The monolithic chip is available in two spe-
cial packages to provide a highly integrated bat-
tery backed-up memory and real time clock
solution.
The M48T35AY/35AV is a non-volatile pin and
function equivalent to any JEDEC standard 32Kb
x8 SRAM. It also easily fits into many ROM,
EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement
for special write timing or limitations on the number
of writes that can be performed.
SNAPHAT (SH)
Battery/Crystal
28
1
SOH28 (MH)
28
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
Figure 1. Logic Diagram
VCC
15
A0-A14
8
DQ0-DQ7
W M48T35AY
M48T35AV
E
G
VSS
AI02797B
May 2000
1/19

1 page




M48T35AY pdf
M48T35AY, M48T35AV
Table 4. AC Measurement Conditions
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no longer
driven.
DATA RETENTION MODE
With valid VCC applied, the M48T35AY/35AV op-
erates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as "don’t care."
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD (min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48T35AY/35AV may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35AY/
35AV for an accumulated period of at least 7 years
when VCC is less than VSO. As system power re-
turns and VCC rises above VSO, the battery is dis-
connected, and the power supply is switched to
external VCC. Write protection continues until VCC
reaches VPFD (min) plus tREC (min). E should be
kept high as VCC rises past VPFD (min) to prevent
inadvertent write cycles prior to processor stabili-
zation. Normal RAM operation can resume tREC
after VCC exceeds VPFD (max).
Also, as VCC rises, the battery voltage is checked.
If the voltage is less than approximately 2.5V, an
internal Battery Not OK (BOK) flag will be set. The
BOK flag can be checked after power up. If the
BOK flag is set, the first write attempted will be
blocked. The flag is automatically cleared after the
first write, and normal RAM operation resumes.
Figure 4. AC Testing Load Circuit
DEVICE
UNDER
TEST
645
CL = 100pF
(or 5pF)
1.75V
CL includes JIG capacitance
AI02586
Figure 9 illustrates how a BOK check routine could
be structured.
For more information on Battery Storage Life refer
to the Application Note AN1012.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register 7FF8h. As
long as a ’1’ remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
5/19

5 Page





M48T35AY arduino
M48T35AY, M48T35AV
Calibrating the Clock
The M48T35AY/35AV is driven by a quartz con-
trolled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed
35 ppm (parts per million) oscillator frequency er-
ror at 25°C, which equates to about ±1.53 minutes
per month. With the calibration bits properly set,
the accuracy of each M48T35AY/35AV improves
to better than ±4 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 11). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T35AY/35AV design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T35AY/35AV may
require. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration byte.
Figure 9. Checking the BOK Flag Status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
IS DATA
COMPLEMENT
OF FIRST
READ?
(BATTERY OK) YES
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
NO (BATTERY LOW)
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
CONTINUE
AI00607
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the Day
Register is set to a '1', and D7 of the Seconds Reg-
ister is a '0' (Oscillator Running), DQ0 will toggle at
512Hz during a read of the Seconds Register. Any
deviation from 512Hz indicates the degree and di-
rection of oscillator frequency shift at the test tem-
perature. For example, a reading of 512.01024Hz
would indicate a +20 ppm oscillator frequency er-
ror, requiring a –10 (WR001010) to be loaded into
the Calibration Byte for correction. Note that set-
ting or changing the Calibration Byte does not af-
fect the Frequency test output frequency.
The FT bit MUST be reset to '0' for normal clock
operations to resume. The FT bit is automatically
Reset on power-up.
For more information on calibration, see the Appli-
cation Note AN934 "TIMEKEEPER Calibration".
11/19

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