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PDF M48T248Y Data sheet ( Hoja de datos )

Número de pieza M48T248Y
Descripción 5.0 or 3.3V / 1024K TIMEKEEPER SRAM
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M48T248Y Hoja de datos, Descripción, Manual

M48T248Y
M48T248V
5.0 or 3.3V, 1024K TIMEKEEPER® SRAM with PHANTOM
FEATURES SUMMARY
5.0V OR 3.3V OPERATING VOLTAGE
Figure 1. 32-pin, DIP Package
REAL TIME CLOCK KEEPS TRACK OF
TENTHS/HUNDREDTHS OF SECONDS,
SECONDS, MINUTES, HOURS, DAYS,
DATE OF THE MONTH, MONTHS, AND
YEARS
AUTOMATIC LEAP YEAR CORRECTION
VALID UP TO THE YEAR 2100
)AUTOMATIC SWITCH-OVER AND
t(sDESELECT CIRCUITRY
CHOICE OF POWER-FAIL DESELECT
ucVOLTAGES:
d(VPFD = Power-fail Deselect Voltage):
ro– M48T248Y: 4.25V VPFD 4.50V
P– M48T248V: 2.80V VPFD 2.97V
teFULL 10% VCC OPERATING RANGE
leOVER 10 YEARS’ DATA RETENTION IN
THE ABSENCE OF POWER
soWATCH FUNCTION IS TRANSPARENT TO
bRAM OPERATION
O128K x 8 NV SRAM DIRECTLY REPLACES
Obsolete Product(s) -VOLATILE STATIC RAM OR EEPROM
32
1
PMDIP32 (PM)
February 2005
1/24

1 page




M48T248Y pdf
M48T248Y, M48T248V
Figure 3. DIP Connections
RST
1
32 VCC
A16 2
31 A15
A14 3
30 NC
A12 4
29 WE
A7 5
28 A13
A6 6
27 A8
A5 7
26 A9
A4
8
M48T248Y
M48T248V
25
A11
A3 9
24 OE
A2 10
23 A10
A1 11
22 CE
A0 12
21 DQ7
DQ0
13
20 DQ6
DQ1
)DQ2
ct(sVSS
14
15
16
19 DQ5
18 DQ4
17 DQ3
AI04662
roduFigure 4. Block Diagram
bsolete PCE
OOE
-WE
t(s)RST
32.768 Hz
CRYSTAL
CONTROL
LOGIC
READ
WRITE
POWER
FAIL
XO
CLOCK/CALENDAR
LOGIC
XI
UPDATE
TIMEKEEPER
REGISTER
SRAM
ducACCESS
roENABLE
SEQUENCE
PDETECTOR
COMPARISON
REGISTER
A0–A16
DQ0–DQ7
ObsoleteDQ0
I/O
BUFFERS
DATA
INTERNAL VCC
VCC
POWER-FAIL
DETECT
LOGIC
VBAT
AI04238
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5 Page





M48T248Y arduino
M48T248Y, M48T248V
Data Retention Mode
Data can be read or written only when VCC is
greater than VPFD. When VCC is below VPFD (the
point at which write protection occurs), the clock
registers and the SRAM are blocked from any ac-
cess. When VCC falls below the Battery Switch
Over threshold (VSO), the device is switched from
VCC to battery backup (VBAT). RTC operation and
SRAM data are maintained via battery backup un-
til power is stable. All control, data, and address
signals must be powered down when VCC is pow-
ered down.
The lithium power source is designed to provide
power for RTC activity as well as RTC and RAM
data retention when VCC is absent or unstable.
The capability of this source is sufficient to power
the device continuously for the life of the equip-
ment into which it has been installed. For specifi-
cation purposes, life expectancy is ten (10) years
at 25°C with the internal oscillator running without
VCC. Each unit is shipped with its energy source
disconnected, guaranteeing full energy capacity.
When VCC is first applied at a level greater than
VPFD, the energy source is enabled for battery
backup operation. The actual life expectancy will
be much longer if no battery energy is used (e.g.,
when VCC is present).
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is estab-
lished by pattern recognition of a serial bit-stream
)of 64 bits which must be matched by executing 64
t(sconsecutive WRITE cycles containing the proper
data on DQ0.
ucAll accesses which occur prior to recognition of the
d64-bit pattern are directed to memory.
roAfter recognition is established, the next 64 READ
Por WRITE cycles either extract or update data in
the clock while disabling the memory.
teData transfer to and from the timekeeping function
leis accomplished with a serial bit-stream under con-
otrol of Chip Enable (CE), Output Enable (OE), and
sWRITE Enable (WE). Initially, a READ cycle using
bthe CE and OE control of the clock starts the pat-
Otern recognition sequence by moving the pointer to
-the first bit of the 64-bit comparison register (see
)Figure 8., page 12).
t(sNext, 64 consecutive WRITE cycles are executed
cusing the CE and WE control of the device. These
u64 WRITE cycles are used only to gain access to
dthe clock. Therefore, any address to the memory
rois acceptable. However, the WRITE cycles gener-
ated to gain access to the Phantom Clock are also
Pwriting data to a location in the mated RAM. The
Obsoletepreferred way to manage this requirement is to set
aside just one address location in RAM as a Phan-
tom Clock scratch pad.
When the first WRITE cycle is executed, it is com-
pared to Bit 1 of the 64-bit comparison register. If
a match is found, the pointer increments to the
next location of the comparison register and
awaits the next WRITE cycle.
If a match is not found, the pointer does not ad-
vance and all subsequent WRITE cycles are ig-
nored. If a READ cycle occurs at any time during
pattern recognition, the present sequence is abort-
ed and the comparison register pointer is reset.
Pattern recognition continues for a total of 64
WRITE cycles as described above until all of the
bits in the comparison register have been
matched. With a correct match for 64-bits, the
Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The
next 64 cycles will cause the Phantom Clock to ei-
ther receive or transmit data on DQ0, depending
on the level of the OE pin or the WE pin. Cycles to
other locations outside the memory block can be
interleaved with CE cycles without interrupting the
pattern recognition sequence or data transfer se-
quence to the Phantom Clock.
11/24

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