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PDF M48T212A Data sheet ( Hoja de datos )

Número de pieza M48T212A
Descripción 3.3V TIMEKEEPER CONTROLLER
Fabricantes ST Microelectronics 
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M48T212A
3.3V TIMEKEEPER® CONTROLLER
PRELIMINARY DATA
s CONVERTS LOW POWER SRAM into
NVRAMs
s YEAR 2000 COMPLIANT (4-Digit Year)
s USES SUPER CAPACITOR or LITHIUM
BATTERY (User Supplied)
s BATTERY LOW FLAG
s INTEGRATED REAL TIME CLOCK,
POWER-FAIL CONTROL CIRCUIT
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WATCHDOG TIMER
s WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T212A: 2.7V VPFD 3.0V
s MICROPROCESSOR POWER-ON RESET
s PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACKED-UP MODE
DESCRIPTION
The M48T212A is a self-contained device that in-
cludes a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.
A built-in 32.768 kHz oscillator (external crystal
controlled) is used for the clock/calendar function.
Access to all TIMEKEEPER functions and the ex-
ternal RAM is the same as conventional byte-wide
SRAM. The 16 TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Control, Calibration, Alarm, Watchdog,
and Flags. Externally attached static RAMs are
controlled by the M48T212A via the E1CON and
E2CON signals (see Table 4).
Automatic backup and write protection for an ex-
ternal SRAM is provided through VOUT, E1CON
and E2CON pins. (Users are urged to insure that
voltage specifications, for both the controller chip
and external SRAM chosen, are similar).
44
1
SOH44 (MH)
Figure 1. Logic Diagram
VCC VCAP
4
A0-A3
A
E
EX
W
G
WDI
RSTIN1
RSTIN2
X0
XI
M48T212A
8
DQ0-DQ7
IRQ/FT
RST
E1CON
E2CON
VCCSW
VOUT
VSS VBAT–
AI03047
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/20

1 page




M48T212A pdf
M48T212A
Table 6. Capacitance (1)
(TA = 25 °C, f = 1 MHz)
Symbol
Parameter
CIN Input Capacitance
COUT (2) Input/Output Capacitance
Note: 1. Sampled only, not 100% tested.
2. Outputs deselected.
Test Condition
VIN = 0V
VOUT = 0V
Min Max Unit
10 pF
10 pF
Table 7. DC Characteristics
(TA = 0 to 70°C; VCC = 3V to 3.6V)
Symbol
Parameter
Test Condition
Min
Typ
Max Unit
ILI (1,2) Input Leakage Current
0V VIN VCC
±1 µA
ILO (1) Output Leakage Current
0V VOUT VCC
±1 µA
ICC Supply Current
Outputs Open
4 10 mA
ICC1 Supply Current (Standby) TTL
E = VIH
3 mA
ICC2 Supply Current (Standby) CMOS
E = VCC –0.2
2 mA
Battery Current OSC ON
IBAT
Battery Current OSC OFF
575 800 nA
100 nA
VIL Input Low Voltage
–0.3
0.8 V
VIH Input High Voltage
2.0 VCC + 0.3 V
Output Low Voltage
VOL
Output Low Voltage (open drain) (3)
IOL = 2.1mA
IOL = 10mA
0.4 V
0.4 V
VOH Output High Voltage
IOH = –1.0mA
2.4
V
VOHB (4) VOH Battery Back-up
IOUT2 = –1.0µA
2.0
3.6 V
IOUT1 (5) VOUT Current (Active)
VOUT1 > VCC –0.3
70 mA
IOUT2 VOUT Current (Battery Back-up)
VOUT2 > VBAT –0.3
100 µA
VPFD Power-fail Deselect Voltage
2.7 2.9
3.0 V
VSO Battery Back-up Switchover Voltage
VPFD –100mV
V
VBAT Battery Voltage
3.0 V
VCAP Capacitor Voltage (6)
VCC
V
Note: 1. Outputs deselected.
2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100Kresistor. WDI internally pulled-down to VSS through 100Kresistor.
3. For IRQ/FT & RST pins (Open Drain).
4. Conditioned outputs (E1CON - E2CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-
rents will reduce battery life.
5. External SRAM must match TIMEKEEPER Controller chip VCC specification.
6. When fully charged.
5/20

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M48T212A arduino
M48T212A
Table 13. TIMEKEEPER Register Map
Address
Fh
Eh
Dh
Ch
Bh
Ah
9h
8h
7h
6h
5h
4h
3h
2h
1h
0h
D7
0
0
0
0
0
ST
W
WDS
AFE
RPT4
RPT3
RPT2
RPT1
WDF
D6 D5 D4
10 Years
0 0 10M
0 10 Date
FT 0
0
0 10 Hours
10 Minutes
10 Seconds
RS
BMB4 BMB3 BMB2
0 ABE Al 10M
RPT5
AI 10 Date
0 AI 10 Hour
Alarm 10 Minutes
Alarm 10 Seconds
1000 Year
AF Y BL
D3 D2 D1 D0
Year
Month
Date: Day of Month
0 Day of Week
Hours (24 Hour Format)
Minutes
Seconds
Calibration
BMB1 BMB0 RB1
RB0
Alarm Month
Alarm Date
Alarm Hour
Alarm Minutes
Alarm Seconds
100 Year
YYYY
Function/Range
BCD Format
Year
Month
Date
Day
Hour
Min
Sec
Control
Watchdog
A Month
A Date
A Hour
A Min
A Sec
Century
Flag
00-99
01-12
01-31
01-7
00-23
00-59
00-59
01-12
01-31
00-23
00-59
00-59
00-99
Keys:
S = Sign Bit
FT = Frequency Test Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag
BMB0-BMB4 = Watchdog Multiplier Bits
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag
AF = Alarm flag
Y = ’1’ or ’0’
The RST signal also remains active during this
time (see Figure 5).
Note: Most low power SRAMs on the market to-
day can be used with the M48T212A TIMEKEEP-
ER Controller. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M48T212A and SRAMs to be Don’t Care once
VCC falls below VPFD(min). The SRAM should also
guarantee data retention down to VCC = 2.0V. The
chip enable access time must be sufficient to meet
the system needs with the chip enable output
propagation delays included.
If the SRAM includes a second chip enable pin
(E2), this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the IBAT value of the M48T212A
to determine the total current requirements for
data retention. The available battery capacity can
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
11/20

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