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PDF M48T201Y Data sheet ( Hoja de datos )
| Número de pieza | M48T201Y | |
| Descripción | 3.3V-5V TIMEKEEPER CONTROLLER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48T201Y
M48T201V
5.0 or 3.3 V TIMEKEEPER® supervisor
Features
■ Converts low power SRAM into NVRAMs
■ Year 2000 compliant
■ Battery low flag
■ Integrated real time clock, power-fail control
circuit, battery and crystal
■ Watchdog timer
■ Choice of write protect voltages
(VPFD = power-fail deselect voltage):
– M48T201Y: VCC = 4.5 to 5.5 V
4.1V ≤ VPFD ≤ 4.5 V
– M48T201V: VCC = 3.0 to 3.6 V
2.7 V ≤ VPFD ≤ 3.0 V
■ Microprocessor power-on reset (valid even
during battery backup mode)
■ Programmable alarm output active in the
battery backed-up mode
■ Packaging includes a 44-lead SOIC and
SNAPHAT® top (to be ordered separately)
■ SOIC package provides direct connection for a
SNAPHAT® top which contains the battery and
crystal
■ RoHS compliant
– Lead-free second level interconnect
SNAPHAT® (SH)
crystal/battery
44
1
SOH44 (MH)
44-pin SOIC
March 2009
Rev 7
1/37
www.st.com
1
1 page  
M48T201Y, M48T201V
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
GCON timing when switching between RTC and external SRAM . . . . . . . . . . . . . . . . . . . . 11
Read cycle timing: RTC and external RAM control signals . . . . . . . . . . . . . . . . . . . . . . . . 12
Write cycle timing: RTC and external RAM control signals. . . . . . . . . . . . . . . . . . . . . . . . . 14
Alarm interrupt reset waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Backup mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RSTIN1 and RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SOH44 – 44-lead plastic small outline, SNAPHAT®, package outline . . . . . . . . . . . . . . . . 31
SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline. . . . . . . . . 32
SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . 33
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5/37
5 Page 
M48T201Y, M48T201V
Operation
Note:
Table 2. Operating modes
Mode
VCC
E GW
Deselect
WRITE
READ
4.5 V to 5.5 V
or
3.0 V to 3.6 V
VIH X
X
VIL X VIL
VIL VIL VIH
READ
VIL VIH VIH
Deselect VSO to VPFD (min)(1)
X
X
X
Deselect
≤ VSO(1)
XXX
1. See Table 14 on page 30 for details.
X = VIH or VIL; VSO = battery backup switchover voltage
DQ7-
DQ0
High-Z
DIN
DOUT
High-Z
High-Z
High-Z
Power
Standby
Active
Active
Active
CMOS standby
Battery backup
2.2 Read mode
The M48T201Y/V executes a READ cycle whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the address inputs (A0-A18) defines which
one of the on-chip TIMEKEEPER® registers or external SRAM locations is to be accessed.
When the address presented to the M48T201Y/V is in the range of 7FFFFh-7FFF0h, one of
the on-board TIMEKEEPER registers is accessed and valid data will be available to the
eight data output drivers within tAVQV after the address input signal is stable, providing that
the E and G access times are also satisfied. If they are not, then data access must be
measured from the latter occurring signal (E or G) and the limiting parameter is either tELQV
for E or tGLQV for G rather than the address access time. When one of the on-chip
TIMEKEEPER registers is selected for READ, the GCON signal will remain inactive
throughout the READ cycle.
When the address value presented to the M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM location will be selected. In this case the G
signal will be passed to the GCON pin, with the specified delay times of tAOEL or tOERL.
Figure 4. GCON timing when switching between RTC and external SRAM
ADDRESS 7FFF0h - 7FFFFh
RTC
G
00000h - 7FFEFh
External SRAM
GCON
E
tAOEL
7FFF0h - 7FFFFh
RTC
00000h - 7FFEFh
External SRAM
tAOEH tOERL
tRO
AI02333
11/37
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M48T201Y.PDF ] | |
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