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PDF M48T128Y Data sheet ( Hoja de datos )
| Número de pieza | M48T128Y | |
| Descripción | 1 Mbit (128 Kb x 8) TIMEKEEPER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48T128Y
M48T128V*
5.0 or 3.3V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM
FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS
■ AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
■ WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T128Y: VCC = 4.5 to 5.5V
4.1V ≤ VPFD ≤ 4.5V
– M48T128V*: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V
■ CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
■ 10 YEARS OF DATA RETENTION AND
CLOCK OPERATION IN THE ABSENCE OF
POWER
■ SELF-CONTAINED BATTERY AND
CRYSTAL IN THE DIP PACKAGE
■ PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
Figure 1. 32-pin PMDIP Module
32
1
PMDIP32 (PM)
Module
* Contact local ST sales office for availability of 3.3V version.
February 2005
1/22
1 page  
Figure 4. Block Diagram
32,768 Hz
CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VPFD
M48T128Y, M48T128V*
8x8
TIMEKEEPER
REGISTERS
131,064 x 8
SRAM ARRAY
A0-A16
DQ0-DQ7
E
W
G
VCC
VSS
AI01804
5/22
5 Page 
M48T128Y, M48T128V*
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (1FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued. All of the TIMEKEEPER registers are updat-
ed simultaneously. A halt will not interrupt an
update in progress. Updating is within a second af-
ter the bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (1FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 11). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers 1FFFFh-1FFF9h to the actual TIME-
KEEPER counters and allows normal operation to
resume. After the WRITE Bit is reset, the next
clock update will occur one second later.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within 1FFF9h. Setting it to
a '1' stops the oscillator. The M48T128Y/V is
shipped from STMicroelectronics with the STOP
Bit set to a '1.' When reset to a '0,' the M48T128Y/
V oscillator starts after one second.
Table 5. Register Map
Data
Address
D7 D6 D5 D4 D3 D2 D1
1FFFFh
10 Years
Year
1FFFEh
0
0
0 10 M
Month
1FFFDh
0
0
10 Date
Date
1FFFCh
0
FT
0
0
0
Day
1FFFBh
0
0
10 Hours
Hours
1FFFAh
0
10 Minutes
Minutes
1FFF9h ST
10 Seconds
Seconds
1FFF8h W
R
Keys: S = SIGN Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
Z = '0' and are Read only
Y = '1' or '0'
S
Calibration
D0
Function/Range
BCD Format
Year
Month
Date
Day
Hours
Minutes
Seconds
Control
00-99
01-12
01-31
01-07
00-23
00-59
00-59
11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet M48T128Y.PDF ] | |
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