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PDF M41TMH6TR Data sheet ( Hoja de datos )

Número de pieza M41TMH6TR
Descripción 512 bit 64b x8 Serial Access TIMEKEEPER SRAM
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M41TMH6TR Hoja de datos, Descripción, Manual

M41T11
512 bit (64b x8) Serial Access TIMEKEEPER® SRAM
s 2.0V to 5.5V SUPPLY VOLTAGE
s COUNTERS for SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS and
CENTURY
s YEAR 2000 COMPLIANT
s SOFTWARE CLOCK CALIBRATION
s AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
s I2C BUS COMPATIBLE
s 56 BYTES of GENERAL PURPOSE RAM
s ULTRA-LOW BATTERY SUPPLY CURRENT
of 1µA
s LOW OPERATING CURRENT of 300µA
s OPERATING TEMPERATURE of –40 to 85°C
s AUTOMATIC LEAP YEAR COMPENSATION
s SPECIAL SOFTWARE PROGRAMMABLE
OUTPUT
s PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT® TOP (to be Ordered Separately)
SNAPHAT (SH)
Battery & Crystal
8
1
SO8 (M)
150mil Width
28
1
SOH28 (MH)
Figure 1. Logic Diagram
VCC VBAT
Table 1. Signal Names
OSCI
Oscillator Input
OCSO
Oscillator Output
FT/OUT
Frequency Test / Output Driver
(Open drain)
SDA
Serial Data Address Input / Output
SCL
Serial Clock
VBAT
Battery Supply Voltage
VCC Supply Voltage
VSS Ground
OSCI
SCL
M41T11
VSS
OSCO
SDA
FT/OUT
AI01000
May 2000
1/19

1 page




M41TMH6TR pdf
M41T11
Table 4. AC Measurement Conditions
Input Rise and Fall Times
5ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref.
Voltages
0.3VCC to 0.7VCC
Note that Output Hi-Z is defined as the point where data is no longer
driven.
2-WIRE BUS CHARACTERISTICS
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock sig-
nals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Figure 4. AC Testing Load Circuit
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI02568
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition, a device that gives out a message is
called "transmitter", the receiving device that gets
the message is called "receiver". The device that
controls the message is called "master". The de-
vices that are controlled by the master are called
"slaves".
Table 5. Capacitance (1, 2)
(TA = 25 °C, f = MHz)
Symbol
Parameter
CIN Input Capacitance (SCL)
COUT (3) Output Capacitance (SDA, FT/OUT)
tLP Low-pass filter input time constant (SDA and SCL)
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled, not 100% tested.
3. Outputs deselected.
Min Max Unit
7 pF
10 pF
250 1000
ns
5/19

5 Page





M41TMH6TR arduino
Figure 10. Write Mode Sequence
M41T11
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (n)
DATA n
BUS ACTIVITY:
SLAVE
ADDRESS
DATA n+1
DATA n+X P
AI00591
Figure 11. Read Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (n)
S
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+X P
AI00899
Figure 12. Alternate Read Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
BUS ACTIVITY:
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+X P
AI00895
11/19

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