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PDF M41T94 Data sheet ( Hoja de datos )
| Número de pieza | M41T94 | |
| Descripción | 512 Bit 64 bit x8 SERIAL RTC SPI SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M41T94
512 Bit (64 bit x8) SERIAL RTC (SPI) SRAM
FEATURES SUMMARY
s 2.7 TO 5.5V OPERATING VOLTAGE
s SERIAL PERIPHERAL INTERFACE (SPI)
s 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
s AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
s CHOICE OF POWER-FAIL DESELECT
VOLTAGES (VCC = 2.7 to 5.5V):
– THS = VSS; 2.55V ≤ VPFD ≤ 2.70V
– THS = VCC; 4.20V ≤ VPFD ≤ 4.50V
s COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY
s 44 BYTES OF GENERAL PURPOSE RAM
s PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
s WATCHDOG TIMER
s MICROPROCESSOR POWER-ON RESET
s BATTERY LOW FLAG
s LOW OPERATING CURRENT OF 2.0mA
s ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (MAX)
s PACKAGING INCLUDES A 28-LEAD SOIC and
SNAPHAT® TOP (to be ordered separately) or
16-LEAD SOIC
s 28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY and
CRYSTAL
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Figure 2. 28-pin SOIC Package
SNAPHAT (SH)
Battery & Crystal
28
1
SOH28 (MH)
June 2003
Rev. 2.0
1/31
1 page  
Figure 3. Logic Diagram
XI (1)
XO (1)
SCL
SDI
E
RSTIN1
RSTIN2
WDI
THS
VCC VBAT (1)
M41T94
RST
IRQ/FT/OUT
SQW
SDO
VSS
AI03683
Note: 1. For SO16 package only.
Figure 4. 16-pin SOIC Connections
XI
XO
RST
WDI
RSTIN1
RSTIN2
VBAT
VSS
1 16
2 15
3 14
4 13
5 M41T94 12
6 11
7 10
89
AI03684
VCC
E
IRQ/FT/OUT
THS
SDI
SQW
SCL
SDO
M41T94
Table 1. Signal Names
E Chip Enable
IRQ/FT/OUT
Interrupt/Frequency Test/Out
Output (Open Drain)
RST
Reset Output (Open Drain)
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
SCL
Serial Clock Input
SDI Serial Data Input
SDO
Serial Data Output
SQW
Square Wave Output
THS
Threshold Select Pin
WDI Watchdog Input
XI (1)
Oscillator Input
XO (1)
Oscillator Output
VBAT (1)
Battery Supply Voltage
VCC
Supply Voltage
VSS
Ground
Note: 1. For SO16 package only.
Figure 5. 28-pin SOIC Connections
SQW
NC
NC
NC
NC
NC
NC
WDI
RSTIN1
RSTIN2
NC
NC
NC
VSS
1
2
3
4
5
6
7
M41T94
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI03685
VCC
E
IRQ/FT/OUT
NC
NC
THS
NC
NC
SCL
NC
RST
SDI
SDO
NC
5/31
5 Page 
M41T94
OPERATION
The M41T94 clock operates as a slave device on
the SPI serial bus. Each memory device is access-
ed by a simple serial interface that is SPI bus com-
patible. The bus signals are SCL, SDI and SDO
(see Table 1, page 5 and Figure 7, page 6). The
device is selected when the Chip Enable input (E)
is held low. All instructions, addresses and data
are shifted serially in and out of the chip. The most
significant bit is presented first, with the data input
(SDI) sampled on the first rising edge of the clock
(SCL) after the Chip Enable (E) goes low. The 64
bytes contained in the device can then be access-
ed sequentially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16.Alarm Registers
17 - 19.Reserved
20. Square Wave Register
21 - 64.User RAM
The M41T94 clock continually monitors VCC for an
out-of tolerance condition. Should VCC fall below
VPFD, the device terminates an access in progress
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from a an out-of-tolerance system. When
VCC falls below VSO, the device automatically
switches over to the battery and powers down into
an ultra low current mode of operation to conserve
battery life. As system power returns and VCC ris-
es above VSO, the battery is disconnected, and the
power supply is switched to external VCC. Write
protection continues until VCC reaches VPFD (min)
plus tREC (min). For more information on Battery
Storage Life refer to Application Note AN1012.
SPI Bus Characteristics
The Serial Peripheral interface (SPI) bus is intend-
ed for synchronous communication between dif-
ferent ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
Clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
The E input is used to initiate and terminate a data
transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
slave (M41T94) devices.
The SCL input, which is generated by the micro-
controller, is active only during address and data
transfer to any device on the SPI bus (see Figure
7, page 6).
The M41T94 can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2, page 7 and Figure
8, page 7).
There is one clock for each bit transferred. Ad-
dress and data bits are transferred in groups of
eight bits. Due to memory size the second most
significant address bit is a Don’t Care (address bit
6).
11/31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M41T94.PDF ] | |
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