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PDF M41T56SH Data sheet ( Hoja de datos )

Número de pieza M41T56SH
Descripción 512 bit 64b x8 Serial Access TIMEKEEPER SRAM
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M41T56
Serial Real Time Clock with 56 bytes NVRAM
Feature summary
Counters for seconds, minutes, hours, day,
date, month, years, and century
32 KHz crystal oscillator integrating load
capacitance (12.5pF) providing exceptional
oscillator stability and high crystal series
resistance operation
Serial interface supports I2C Bus (400kHz
protocol)
Ultra-low battery supply current of 450nA
(typ@3V)
5V ±10% supply voltage
Timekeeping down to 2.5V
Automatic power-fail detect and switch circuitry
56 bytes of general purpose RAM
Software clock calibration to compensate
crystal deviation due to temperature
Automatic leap year compensation
Operating temperature of –40 to 85°C
Packaging options include:
– 28-lead SOIC and SNAPHAT® TOP (to be
ordered separately)
– SO8N
8
1
SO8N (M) 150mil width
SNAPHAT (SH) battery & crystal
28
1
SOH28 (MH)
October 2006
Rev 5
1/28
www.st.com
1

1 page




M41T56SH pdf
M41T56
1 Summary description
Summary description
Caution:
The M41T56 is a low power, Serial Real Time Clock with 56 bytes of NVRAM. A built-in
32,768Hz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used for
the clock/calendar function and are configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a two-line, bi-directional bus. The built-in
address register is incremented automatically after each WRITE or READ data byte.
The M41T56 clock has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply during power failures. The energy needed to
sustain the RAM and clock operations can be supplied from a small lithium coin cell.
Typical data retention time is in excess of 10 years with a 50mAh, 3V lithium cell. The
M41T56 is supplied in an 8-lead Plastic SOIC package or a 28-lead SNAPHAT® package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing containing the battery and crystal. The unique
design allows the SNAPHAT battery package to be mounted on top of the SOIC package
after the completion of the surface mount process. Insertion of the SNAPHAT housing after
reflow prevents potential battery and crystal damage due to the high temperatures required
for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4Txx-
BR12SH” (see Table 16 on page 26).
Do not place the SNAPHAT battery/crystal package “M4Txx-BR12SH” in conductive foam
as this will drain the lithium button-cell battery.
Figure 1. Logic diagram
VCC VBAT
OSCI
SCL
M41T56
OSCO
SDA
FT/OUT
VSS
AI02304B
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M41T56SH arduino
M41T56
Operation
Table 2.
Symbol
AC characteristics
Parameter(1)
Min Max Unit
fSCL
tLOW
tHIGH
tR
tF
tHD:STA
SCL clock frequency
Clock low period
Clock high period
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
(after this period the first clock pulse is generated)
0 100 kHz
4.7 µs
4 µs
1 µs
300 ns
4 µs
START condition setup time
tSU:STA (only relevant for a repeated start condition)
4.7
µs
tSU:DAT Data setup time
tHD:DAT(2) Data hold time
tSU:STO STOP condition setup time
tBUF
Time the bus must be free before a new transmission
can start
250
0
4.7
4.7
ns
µs
µs
µs
1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling
edge of SCL.
2.2 READ mode
In this mode, the master reads the M41T56 slave after setting the slave address (see
Figure 8 on page 12 and Figure 9 on page 12). Following the WRITE Mode Control Bit (R/W
= 0) and the Acknowledge Bit, the word address An is written to the on-chip address pointer.
Next the START condition and slave address are repeated, followed by the READ Mode
Control Bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The
data byte which was addressed will be transmitted and the master receiver will send an
Acknowledge Bit to the slave transmitter. The address pointer is only incremented on
reception of an Acknowledge Bit. The M41T56 slave transmitter will now place the data byte
at address An + 1 on the bus. The master receiver reads and acknowledges the new byte
and the address pointer is incremented to An + 2. This cycle of reading consecutive
addresses will continue until the master receiver sends a STOP condition to the slave
transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T56
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer, see Figure 10 on page 12.
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