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PDF U2781B Data sheet ( Hoja de datos )
| Número de pieza | U2781B | |
| Descripción | Frequency Synthesizer | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Frequency Synthesizer
U2781B
Description
The programmable frequency synthesizer IC U2781B for
µP-controlled applications is realized with Atmel
Wireless & Microcontrollers’ advanced UHF process
which is very suitable for combinations of fast ECL logic
and low-current I2L logic. The benefits are high input
sensitivity combined with low power consumption and
therefore small packages (SSO20). This makes the
device a perfect choice for cordless phones and handheld
cellular radio sets up to 1.1 GHz.
Electrostatic sensitive device.
Observe precautions for handling.
Features
D Very low current consumption (typ. 3 V/ 5 mA)
D Supply-voltage range: 2.7 to 5.5 V
D Max. input frequency: 1.1 GHz
D Programmable prescaler 64/ 65 or 128/ 129
D Controlled by 3-wire bus with fclock up to 500 kHz
D Status output for PLL lock/ unlock condition
D Very fast phase detector
D SSO20 package
D ESD protection in accordance with MIL-STD. 883
method 3015 class 2
Benefits
D Very low current consumption extends talk time
D Few external components and SSO package save costs
and space
Block Diagram
Osci
Osco
VS
GND
Clock
Data
Enable
1
3
5
7
11
13
14
Oscillator
1-bit latch
load control
RFi
10
Prescaler
64/65
128/129
14-bit
reference counter
15-bit latch
18-bit
shift register
18-bit latch
7-bit
swallow
counter
11-bit
main
counter
Phase
detector
Charge
pump
Mo
17
LDo
8
VSCP
4
CP
6
15 PS
U2781B
Figure 1. Block diagram
Rev. A4, 11-Sep-00
1 (10)
1 page  
U2781B
Functional Description
The reference- and the programmable counter can be
programmed by the 3-wire bus (Clock, Data and Enable).
The Data Signal is transferred bit by bit into the shift
register during the rising edge, starting with the MSB-bit.
As soon as the enable signal is in high condition, the
content of the shift register will be taken over either into
the 15-bit reference counter latch (C = H) or into the
18-bit latch of the programmable counter (C = L)
ÁÁÁRLÁÁÁeCSfBeÁÁÁreÁÁÁRn0cÁÁÁe CRÁÁÁo1uÁÁÁnRtÁÁÁe2rÁÁÁ(1R5ÁÁÁ3-bÁÁÁitRsÁÁÁ4hifÁÁÁtRr5ÁÁÁegiÁÁÁsRte6ÁÁÁr) ÁÁÁR7ÁÁÁÁÁÁR8ÁÁÁÁÁÁR9 ÁÁÁRÁÁÁ10ÁÁÁRÁÁÁ11 ÁÁÁRÁÁÁ12 ÁÁÁR1ÁÁÁ3 ÁÁÁMPSSÁÁÁCB ÁÁÁ
C: Control bit High
PSC: Prescaler scaling factor bit: High – 64/65
Low – 128/129
R0 to R13:
SPSC = 64 or 128
These bits are setting the reference counter SR
SR = R0 20 + R1 21 + to + R12 212 + R13
permitted scaling factors for SR: 4 to 16383
213
Programmable Counter (18-bit shift register)
ÁÁÁÁÁÁLCSBÁÁÁÁÁÁS0ÁÁÁSÁÁÁ1 ÁÁÁS2ÁÁÁSÁÁÁ3 ÁÁÁS4ÁÁÁSÁÁÁ5 ÁÁÁS6ÁÁÁMÁÁÁ0 ÁÁÁMÁÁÁ1 MÁÁÁ2ÁÁÁMÁÁÁ3 ÁÁÁM4ÁÁÁMÁÁÁ5 ÁÁÁM6ÁÁÁMÁÁÁ7 ÁÁÁM8ÁÁÁMÁÁÁ9 ÁÁÁMMSÁÁÁ1B0 ÁÁÁ
C: Control bit Low
S0 to S6:
These bits are setting the swallow counter SS.
SS = S0 20 + S1 21 + to + S5 25 + S6 26
permitted scaling factors for SS: 0 to 127, SS < SM
M0 to M10 : These bits are setting the main counter SM.
SM = M0 20 + M1 21 + to + M9 29 + M10
permitted scaling factors for SM: 4 to 2047
210
Total scaling factor SP of the programmable counter
SP = (SPSC SM) + SS Condition: SS < SM
VCO Frequency
fVCO = ((SPSC
SM) + SS)
fRefOsc / SR
Rev. A4, 11-Sep-00
5 (10)
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet U2781B.PDF ] | |
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