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PDF MAX1108 Data sheet ( Hoja de datos )
| Número de pieza | MAX1108 | |
| Descripción | Single-Supply / Low-Power / 2-Channel / Serial 8-Bit ADCs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-1399; Rev 0; 10/98
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
General Description
The MAX1108/MAX1109 low-power, 8-bit, dual-channel,
analog-to-digital converters (ADCs) feature an internal
track/hold (T/H) voltage reference, clock, and serial inter-
face. The MAX1108 is specified from +2.7V to +3.6V and
consumes only 105µA. The MAX1109 is specified from
+4.5V to +5.5V and consumes only 130µA. The analog
inputs are software configurable, allowing unipolar/bipolar
and single-ended/differential operation; battery monitor-
ing capability is also included.
The full-scale analog input range is determined by the
internal reference of +2.048V (MAX1108) or +4.096V
(MAX1109), or by an externally applied reference rang-
ing from 1V to VDD. The MAX1108/MAX1109 also feature
a software power-down mode that reduces power con-
sumption to 0.5µA when the device is not in use. The
4-wire serial interface directly connects to SPI™, QSPI™,
and MICROWIRE™ devices without external logic.
Conversions up to 50ksps are performed using either the
internal clock or an external serial-interface clock.
The MAX1108 and MAX1109 are available in a 10-pin
µMAX package with a footprint that is just 20% of an
8-pin plastic DIP.
Applications
Portable Data Logging
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Solar-Powered Remote Systems
4–20mA-Powered Remote Systems
Receive-Signal Strength Indicators
Pin Configuration
Features
o Single Supply: +2.7V to +3.6V (MAX1108)
+4.5V to +5.5V (MAX1109)
o Low Power: 105µA at +3V and 50ksps
0.5µA in Power-Down Mode
o Software-Configurable Unipolar or Bipolar Inputs
o Input Voltage Range: 0 to VDD
o Internal Track/Hold
o Internal Reference: +2.048V (MAX1108)
+4.096V (MAX1109)
o Reference Input Range: 1V to VDD
o SPI/QSPI/MICROWIRE-Compatible Serial Interface
o VDD Monitoring Mode
o Small 10-Pin µMAX Package
PART
MAX1108CUB
MAX1108EUB
MAX1109CUB
MAX1109EUB
Ordering Information
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
10 µMAX
10 µMAX
10 µMAX
10 µMAX
Functional Diagram
CS
SCLK
DIN
INPUT
SHIFT
REGISTER
VDD
OUTPUT
SHIFT
REGISTER
DOUT
TOP VIEW
VDD 1
CH0 2
CH1 3
GND 4
REF 5
MAX1108
MAX1109
µMAX
10 SCLK
9 DOUT
8 DIN
7 CS
6 COM
MAX1108
MAX1109
CONTROL
LOGIC
INTERNAL
OSCILLATOR
CH0 ANALOG
T/H
SAR
CH1 INPUT
MUX
COM
CHARGE
INTERNAL
REFERENCE
REDISTRIBUTION
DAC
REF
GND
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1109 (continued)
(VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values
are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock)
Signal-to-Noise Plus Distortion SINAD
49 dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70 dB
Spurious Free Dynamic Range
Small-Signal Bandwidth
Full-Power Bandwidth
ANALOG INPUTS
Input Voltage Range (Note 4)
SFDR
BW-3dB -3dB rolloff
VCH_
Unipolar input, VCOM = 0
Bipolar input, VCOM or VCH1 = VREF / 2,
referenced to COM or CH1
68 dB
1.5 MHz
0.8 MHz
0 VREF
±VREF / 2
V
Multiplexer Leakage Current
Input Capacitance
TRACK/HOLD
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
On/off-leakage current,
VCH = 0 or VDD
CIN
tCONV
tACQ
Internal clock
External clock, 500kHz, 10 sclks/conv
External clock, 2MHz
External Clock Frequency Range
INTERNAL REFERENCE
Output Voltage
REF Short-Circuit Current
REF Tempco
Load Regulation
Capacitive Bypass at REF
EXTERNAL REFERENCE
Input Voltage Range
Input Current
VREF
IREFSC
For data transfer only
0 to 0.5mA (Note 7)
+4.096V at REF, full scale,
500kHz external clock
±0.01
18
±1
µA
pF
35
µs
20
1 µs
10 ns
<50 ps
400 kHz
50 500 kHz
2 MHz
3.936
1
4.096
5
±50
2.5
4.256
V
mA
ppm/°C
mV
µF
1.0 VDD + 0.05 V
1 20 µA
_______________________________________________________________________________________ 5
5 Page 
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
holding capacitor CHOLD through RIN. At the end of
acquisition the T/H switch opens and CHOLD is con-
nected to COM, retaining charge on CHOLD as a sam-
ple of the signal at CH0, and the difference between
CH0 and COM is the converted signal. Once conver-
sion is complete, the T/H returns immediately to its
tracking mode. This procedure holds for the different
combinations summarized in Table 2.
The time available for the T/H to acquire an input signal
(tACQ) is determined by the clock frequency, and is 1µs
at the maximum clock frequency of 2MHz. The acquisi-
tion time is also the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ = 6(RS + RIN)18pF
where RIN = 6.5kΩ, RS = the source impedance of
the input signal, and tACQ is never less than 1µs.
Note that source impedances below 2.7kΩ do not
significantly affect the AC performance of the ADC at
the maximum clock speed. If the input-source imped-
ance is higher than 3kΩ, the clock speed must be
reduced accordingly.
Pseudo-Differential Input
The MAX1108/MAX1109 input configuration is pseudo-
differential to the extent that only the signal at the sam-
pled input (SI) is stored in the holding capacitor
(CHOLD). The reference input (RI) must remain stable
within ±0.5LSB (±0.1LSB for best results) in relation to
GND during a conversion. Sampled input and refer-
ence input configuration is determined by bit6–bit4
(SEL2–SEL0) of the control byte (Table 2).
If a varying signal is applied at the selected reference
input, its amplitude and frequency need to be limited.
The following equations determine the relationship
between the maximum signal amplitude and its fre-
quency to maintain ±0.5LSB accuracy:
Assuming a sinusoidal signal at the reference input
vRI = VRIsin(2πft)
the maximum voltage variation is determined by:
max dvRI
dt
= 2πf ⋅ vRI ≤
1 LSB
tCONV
=
VREF
28 tCONV
a 60Hz signal at RI with an amplitude of 1.2V will gener-
ate a ±0.5LSB of error. This is with a 35µs conversion
time (maximum tCONV in internal conversion mode) and
a reference voltage of +4.096V. When a DC reference
voltage is used at RI, connect a 0.1µF capacitor to
GND to minimize noise at the input.
The input configuration selection also determines
unipolar or bipolar conversion mode. The common-
mode input range of CH0, CH1, and COM is 0 to +VDD.
In unipolar mode, full scale is achieved when (SI - RI) =
VREF; in bipolar mode, full scale is achieved when (SI
- RI) = VREF / 2. In unipolar mode, SI must be higher
than RI; in bipolar mode, SI can span above and below
RI provided that it is within the common-mode range.
Conversion Process
The comparator negative input is connected to the auto-
zero rail. Since the device requires only a single supply,
the ZERO node at the input of the comparator equals
VDD/2. The capacitive DAC restores node ZERO to have
0V difference at the comparator inputs within the limits
of 8-bit resolution. This action is equivalent to transfer-
ring a charge of 18pF(VIN+ - VIN-) from CHOLD to the
binary-weighted capacitive DAC which, in turn, forms a
digital representation of the analog-input signal.
Input Voltage Range
Internal protection diodes that clamp the analog input
to VDD and AGND allow the channel input pins (CH0,
CH1, and COM) to swing from (AGND - 0.3V) to (VDD +
0.3V) without damage. However, for accurate conver-
sions, the inputs must not exceed (VDD + 50mV) or be
less than (GND - 50mV).
If the analog input voltage on an “off” channel
exceeds 50mV beyond the supplies, the current
should be limited to 2mA to maintain conversion
accuracy on the “on” channel.
The MAX1108/MAX1109 input range is from 0 to VDD;
unipolar or bipolar conversion is available. In unipolar
mode, the output code is invalid (code zero) when a
negative input voltage (or a negative differential input
voltage) is applied. The reference input-voltage range
at REF is from 1V to (VDD + 50mV.)
Input Bandwidth
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Serial Interface
The MAX1108/MAX1109 have a 4-wire serial interface.
The CS, DIN, and SCLK inputs are used to control the
device, while the three-state DOUT pin is used to
access the result of conversion.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX1108.PDF ] | |
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