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PDF MAX1106 Data sheet ( Hoja de datos )

Número de pieza MAX1106
Descripción Single-Supply / Low-Power / Serial 8-Bit ADCs
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX1106 Hoja de datos, Descripción, Manual

19-1432; Rev 0; 3/99
Single-Supply, Low-Power,
Serial 8-Bit ADCs
General Description
The MAX1106/MAX1107 low-power, 8-bit, single-channel,
analog-to-digital converters (ADCs) feature an internal
track/hold (T/H), voltage reference, clock, and serial inter-
face. The MAX1106 is specified from +2.7V to +3.6V and
consumes only 96µA. The MAX1107 is specified from
+4.5V to +5.5V and consumes only 107µA. The analog
inputs are pin-configurable, allowing unipolar and single-
ended or differential operation.
The full-scale analog input range is determined by the
internal reference of +2.048V (MAX1106) or +4.096V
(MAX1107), or by an externally applied reference rang-
ing from 1V to VDD. The MAX1106/MAX1107 also feature
a pin-selectable power-down mode that reduces power
consumption to 0.5µA when the device is not in use. The
3-wire serial interface directly connects to SPI™, QSPI™,
and MICROWIRE™ devices without external logic.
Conversions up to 25ksps are performed using the inter-
nal clock.
The MAX1106/MAX1107 are available in a 10-pin µMAX
package with a footprint that is just 20% of an
8-pin plastic DIP.
Applications
Portable Data Logging
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Solar-Powered Remote Systems
4–20mA-Powered Remote Systems
Receive-Signal-Strength Indicators
Pin Configuration
TOP VIEW
VDD 1
IN+ 2
IN- 3
GND 4
REFOUT 5
MAX1106
MAX1107
µMAX
10 SCLK
9 DOUT
8 SHDN
7 CONVST
6 REFIN
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Features
o Single Supply: +2.7V to +3.6V (MAX1106)
+4.5V to +5.5V (MAX1107)
o Low Power: 96µA at +3V and 25ksps
0.5µA in Power-Down Mode
o Pin-Programmable Configuration
o 0 to VDD Input Voltage Range
o Internal Track/Hold
o Internal Reference: +2.048V (MAX1106)
+4.096V (MAX1107)
o 1V to VDD Reference Input Range
o SPI/QSPI/MICROWIRE-Compatible Serial Interface
o Small 10-Pin µMAX Package
PART
MAX1106CUB
MAX1106EUB
MAX1107CUB
MAX1107EUB
Ordering Information
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
10 µMAX
10 µMAX
10 µMAX
10 µMAX
CONVST
SCLK
SHDN
Functional Diagram
VDD
MAX1106
MAX1107
OUTPUT
SHIFT
REGISTER
DOUT
IN+
IN-
REFOUT
REFIN
CONTROL
LOGIC
ANALOG
INPUT
MUX
INTERNAL
REFERENCE
INTERNAL
OSCILLATOR
T/H SAR
CHARGE
REDISTRIBUTION
DAC
GND
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.

1 page




MAX1106 pdf
Single-Supply, Low-Power,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1107
(VDD = +4.5V to +5.5V; IN- = GND; fSCLK = 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +4.096V reference at
REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DC ACCURACY
Resolution
8 Bits
Relative Accuracy (Note 1)
INL
±0.15 ±0.5 LSB
Differential Nonlinearity
DNL No missing codes over temperature
±1 LSB
Offset Error
±0.2 ±1 LSB
Gain Error (Note 3)
±1 LSB
Gain Temperature Coefficient
±0.8
ppm/°C
Total Unadjusted Error
TUE
TA = +25°C
TA = TMIN to TMAX
DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 25ksps conversion rate)
±1
LSB
±0.5
Signal-to-Noise Plus Distortion SINAD
49 dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70 dB
Spurious-Free Dynamic Range SFDR
68 dB
Small-Signal Bandwidth
Full-Power Bandwidth
BW-3dB -3dB rolloff
1.5 MHz
0.8 MHz
ANALOG INPUTS
Input Voltage Range (Note 4)
VIN_ VIN+ to VIN-
0
VREFIN
V
Input Leakage Current
On/off-leakage current,
VIN+ or VIN- = 0 or VDD
±0.01 ±1
µA
Input Capacitance
TRACK/HOLD
CIN
18 pF
Conversion Time
Track/Hold Acquisition Time
Aperture Delay
tCONV
tACQ
Figure 7
35 µs
1 µs
10 ns
Aperture Jitter
<50 ps
Internal Clock Frequency
400 kHz
External Clock Frequency Range
For data transfer only
2 MHz
INTERNAL REFERENCE
Output Voltage
REF Short-Circuit Current
REF Tempco
VREFOUT
IREFSC
3.936
4.096
5
±50
4.256
V
mA
ppm/°C
Load Regulation
0 to 0.5mA (Note 6)
4 mV
Capacitive Bypass at REFOUT
1 µF
_______________________________________________________________________________________ 5

5 Page





MAX1106 arduino
Single-Supply, Low-Power,
Serial 8-Bit ADCs
where RIN = 6.5k, RS = the source impedance of the
input signal, and tACQ must never be less than 1µs.
This is easily achieved by respecting the minimum
CONVST high interval required and the time required to
clock the data out.
Pseudo-Differential Input
The MAX1106/MAX1107 input configuration is pseudo-
differential to the extent that only the signal at the sam-
pled input (IN+) is stored in the holding capacitor
(CHOLD). IN- must remain stable within ±0.5LSB
(±0.1LSB for best results) in relation to GND during a
conversion.
If a varying signal is applied at the IN- input, its ampli-
tude and frequency need to be limited. The following
equations determine the relationship between the maxi-
mum signal amplitude and its frequency to maintain
±0.5LSB accuracy:
Assuming a sinusoidal signal at the IN- input,
( )υIN- = VIN- sin(2πft)
under the maximum voltage variation is determined by
( )max ∆υIN- = 2πf VIN- 1 LSB = VREFIN
t
tCONV
28 tCONV
a 60Hz signal at IN- with an amplitude of 1.2V will
generate ±0.5LSB of error. This is with a 35µs conver-
sion time (maximum tCONV) and a reference voltage of
4.096V. When a DC reference voltage is used at IN-,
connect a 0.1µF capacitor from IN_ to GND to minimize
noise at the input.
The common-mode input range of IN+ and IN- is GND
to +VDD. Full-scale is achieved when (VIN- - VIN+) =
VREFIN. VIN+ must be higher than VIN-.
Conversion Process
The comparator negative input is connected to the auto-
zero rail. Since the device requires only a single supply,
the ZERO node at the input of the comparator equals
VDD/2. The capacitive DAC restores node ZERO to have
0V difference at the comparator inputs within the limits
of 8-bit resolution. This action is equivalent to transfer-
ring a charge of 18pF(VIN+ - VIN-) from CHOLD to the
binary-weighted capacitive DAC which, in turn, forms a
digital representation of the analog-input signal.
Input Voltage Range
Internal protection diodes that clamp the analog input to
VDD and GND allow the input pins (IN+ and IN-) to swing
from (GND - 0.3V) to (VDD + 0.3V) without damage.
However, for accurate conversions, the inputs must not
exceed (VDD + 50mV) or be less than (GND - 50mV).
The MAX1106/MAX1107 input range is from GND to
VDD. The output code is invalid (code zero) when a
negative input voltage (or a negative differential input
voltage) is applied. The reference input-voltage range
at REFIN is from 1V to (VDD + 50mV).
Input Bandwidth
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Serial Interface
The MAX1106/MAX1107 have a 3-wire serial interface.
The CONVST and SCLK inputs are used to control the
device, while the three-state DOUT pin is used to
access the result of conversion.
The serial interface provides easy connection to micro-
controllers with SPI, QSPI, and MICROWIRE serial inter-
faces at clock rates up to 2MHz. For SPI and QSPI, set
CPOL = CPHA = 0 in the SPI control registers of the
microcontroller. Figure 5 shows the MAX1106/MAX1107
common serial-interface connections.
Digital Inputs and Outputs
The logic levels of the MAX1106/MAX1107 digital
inputs are set to accept voltage levels from both 3V
and 5V systems regardless of the supply voltages.
A conversion is started by toggling CONVST. CONVST
idles low and needs to be set high for at least 1µs to
perform the autozero adjustment. CONVST must remain
low during conversion and until the result of conversion
has been clocked out.
After CONVST is set low, allow 35µs for the conversion
to be completed. While the internal conversion is in
progress DOUT is low. Conversion is controlled by an
internal 400kHz oscillator. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 9). Data is
clocked out at SCLK’s falling edge in MSB-first format
at rates up to 2MHz. Once all data bits are clocked out,
DOUT goes high impedance at the falling edge of the
eighth SCLK pulse.
______________________________________________________________________________________ 11

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