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PDF MAX1091 Data sheet ( Hoja de datos )
| Número de pieza | MAX1091 | |
| Descripción | 10-Bit ADCs | |
| Fabricantes | Maxim Integrated | |
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19-1638; Rev 2; 12/02
EVAALVUAAILTAIOBNLEKIT
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
General Description
The MAX1091/MAX1093 low-power, 10-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. They operate
with a single +3V analog supply and feature a VLOGIC
pin that allows them to interface directly with a +1.8V to
+3.6V digital supply.
Power consumption is only 5.7mW (VDD = VLOGIC) at the
maximum sampling rate of 250ksps. Two software-selec-
table power-down modes enable the MAX1091/
MAX1093 to be shut down between conversions;
accessing the parallel interface returns them to normal
operation. Powering down between conversions can cut
supply current to under 10µA at reduced sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1091 has
eight input channels and the MAX1093 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1091/MAX1093 tri-states INT when CS goes
high. Refer to MAX1061/MAX1063 if tri-stating INT is not
desired.
The MAX1091 is available in a 28-pin QSOP package,
while the MAX1093 is available in a 24-pin QSOP. For
pin-compatible +5V, 10-bit versions, refer to the
MAX1090/MAX1092 data sheet.
Industrial Control Systems
Applications
Data Logging
Energy Management
Patient Monitoring
Data-Acquisition Systems Touch Screens
Ordering Information
PART
TEMP RANGE
MAX1091ACEI
MAX1091BCEI
MAX1091AEEI
MAX1091BEEI
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 QSOP
28 QSOP
28 QSOP
28 QSOP
INL
(LSB)
±0.5
±1
±0.5
±1
Features
o 10-Bit Resolution, ±0.5 LSB Linearity
o +3V Single-Supply Operation
o User-Adjustable Logic Level (+1.8V to +3.6V)
o Internal +2.5V Reference
o Software-Configurable, Analog Input Multiplexer
8-Channel Single-Ended/
4-Channel Pseudo-Differential (MAX1091)
4-Channel Single-Ended/
2-Channel Pseudo-Differential (MAX1093)
o Software-Configurable, Unipolar/Bipolar Inputs
o Low Power
1.9mA (250ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)
o Internal 3MHz Full-Power Bandwidth Track/Hold
o Byte-Wide Parallel (8 + 2) Interface
o Small Footprint: 28-Pin QSOP (MAX1091)
24-Pin QSOP (MAX1093)
Pin Configurations
TOP VIEW
HBEN 1
D7 2
D6 3
D5 4
D4 5
D3 6
MAX1093
24 VLOGIC
23 VDD
22 REF
21 REFADJ
20 GND
19 COM
D2 7
D1/D9 8
18 CH0
17 CH1
D0/D8 9
INT 10
RD 11
WR 12
16 CH2
15 CH3
14 CS
13 CLK
QSOP
Pin Configurations continued at end of data sheet.
Ordering Information continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
RD Rise to Output Disable
RD Fall to Output Data Valid
HBEN to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
SYMBOL
tTR
tDO
tDO1
tINT1
tDO2
CONDITIONS
CLOAD = 20pF (Figure 1)
CLOAD = 20pF (Figure 1)
CLOAD = 20pF (Figure 1)
CLOAD = 20pF (Figure 1)
CLOAD = 20pF (Figure 1)
MIN TYP MAX UNITS
20 70 ns
20 70 ns
20 110 ns
100 ns
110 ns
Note 1: Tested at VDD = +3V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
DOUT
3kΩ
CLOAD
20pF
VLOGIC
3kΩ
DOUT
CLOAD
20pF
a) HIGH-Z TO VOH AND VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________ 5
5 Page 
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle aborts the conversion and starts a
new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval ends (three external
cycles or approximately 1µs in internal clock mode)
(Figure 4). Note that, when the internal acquisition is
combined with the internal clock, the aperture jitter can
be as high as 200ps. Internal clock users wishing to
achieve the 50ps jitter specification should always use
external acquisition mode.
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0, terminates
acquisition and starts conversion on WR’s rising edge
(Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see the Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
Reading a Conversion
A standard interrupt signal INT is provided to allow the
MAX1091/MAX1093 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
Table 1. Control Byte Functional Description
BIT
D7, D6
D5
D4
D3
D2, D1, D0
NAME
FUNCTION
PD1 and PD0 select the various clock and power-down modes.
0 0 Full Power-Down Mode. Clock mode is unaffected.
PD1, PD0
0
1 Standby Power-Down Mode. Clock mode is unaffected.
1 0 Normal Operation Mode. Internal clock mode selected.
1 1 Normal Operation Mode. External clock mode selected.
ACQMOD
SGL/DIF
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (see Tables 2 and 3).
UNI/BIP
A2, A1, A0
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the sig-
nal can range from -VREF/2 to +VREF/2.
Address bits A2, A1, A0 select which of the 8/4 (MAX1091/MAX1093) channels are to be converted
(see Tables 3 and 4).
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX1091.PDF ] | |
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