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PDF MAX1080 Data sheet ( Hoja de datos )

Número de pieza MAX1080
Descripción 300ksps/400ksps / Single-Supply / Low-Power / 8-Channel / Serial 10-Bit ADCs with Internal Reference
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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19-1685; Rev 0; 5/00
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
General Description
The MAX1080/MAX1081 10-bit analog-to-digital convert-
ers (ADCs) combine an 8-channel analog-input multiplex-
er, high-bandwidth track/hold (T/H), and serial interface
with high conversion speed and low power consumption.
The MAX1080 operates from a single +4.5V to +5.5V sup-
ply; the MAX1081 operates from a single +2.7V to +3.6V
supply. Both devices’ analog inputs are software config-
urable for unipolar/bipolar and single-ended/pseudo-dif-
ferential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1080/
MAX1081 use an external serial-interface clock to perform
successive-approximation analog-to-digital conversions.
The devices feature an internal +2.5V reference and a ref-
erence-buffer amplifier with a ±1.5% voltage-adjustment
range. An external reference with a 1V to VDD1 range may
also be used.
The MAX1080/MAX1081 provide a hard-wired SHDN pin
and four software-selectable power modes (normal opera-
tion, reduced power (REDP), fast power-down (FASTPD),
and full power-down (FULLPD)). These devices can be
programmed to automatically shut down at the end of a
conversion or to operate with reduced power. When using
the power-down modes, accessing the serial interface
automatically powers up the devices, and the quick turn-
on time allows them to be shut down between all conver-
sions. This technique can cut supply current below 100mA
at lower sampling rates.
The MAX1080/MAX1081 are available in a 20-pin TSSOP
package. These devices are higher-speed versions of the
MAX148/MAX149. For more information, refer to the
respective data sheet.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
Typical Operating Circuit appears at end of data sheet.
Features
o 8-Channel Single-Ended or 4-Channel
Pseudo-Differential Inputs
o Internal Multiplexer and Track/Hold
o Single-Supply Operation
+4.5V to +5.5V (MAX1080)
+2.7V to +3.6V (MAX1081)
o Internal +2.5V Reference
o 400ksps Sampling Rate (MAX1080)
o Low Power: 2.5mA (400ksps)
1.3mA (REDP)
0.9mA (FASTPD)
2µA (FULLPD)
o SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
o Software-Configurable Unipolar or Bipolar Inputs
o 20-Pin TSSOP Package
Ordering Information
PART
TEMP.
RANGE
PIN-
PACKAGE
INL
(LSB)
MAX1080ACUP 0°C to +70°C 20 TSSOP
±1/2
MAX1080BCUP 0°C to +70°C 20 TSSOP
±1
MAX1080AEUP -40°C to +85°C 20 TSSOP
±1/2
Ordering Information continued at end of data sheet.
Pin Configuration
TOP VIEW
CH0 1
CH1 2
CH2 3
CH3 4
CH4 5
CH5 6
CH6 7
CH7 8
COM 9
SHDN 10
MAX1080
MAX1081
20 VDD1
19 VDD2
18 SCLK
17 CS
16 DIN
15 SSTRB
14 DOUT
13 GND
12 REFADJ
11 REF
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
TSSOP
________________________________________________________________ Maxim Integrated Products 1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.

1 page




MAX1080 pdf
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1081 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
SYMBOL
CONDITIONS
tCONV
tACQ
Normal operating mode
Normal operating mode
Serial Clock Frequency
fSCLK
Duty Cycle
ANALOG INPUTS (CH7–CH0, COM)
Input Voltage Range, Single
Ended and Differential (Note 6)
VCH_
Normal operating mode
Unipolar, VCOM = 0
Bipolar, VCOM or VCH_ = VREF/2,
referenced to COM or CH_
Multiplexer Leakage Current
Input Capacitance
INTERNAL REFERENCE
REF Output Voltage
REF Short-Circuit Current
On/off leakage current, VCH_ = 0 or VDD1
VREF TA = +25°C
REF Output Temperature
Coefficient
TC VREF
Load Regulation (Note 7)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Input Range
0 to 0.75mA output load
For small adjustments, from 1.22V
REFADJ Buffer Disable
Threshold
To power down the internal reference
Buffer Voltage Gain
EBXufTfeErRVNoAltaLgReEGFaEinRENCE (reference buffer disabled, reference applied to REF)
REF Input Voltage Range
(Note 8)
REF Input Current
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
VINH
Input Low Voltage
VINL
Input Hysteresis
VHYST
Input Leakage
IIN
Input Capacitance
CIN
VREF = 2.500V, fSCLK = 4.8MHz
VREF = 2.500V, fSCLK = 0
In power-down mode, fSCLK = 0
VIN = 0 or VDD2
MIN TYP MAX UNITS
3.3 µs
625 ns
10 ns
<50 ps
0.5 4.8 MHz
40 60 %
VREF
±VREF/2
±0.001 ±1
18
V
µA
pF
2.480 2.500 2.520
15
V
mA
±15 ppm/°C
0.1 2.0
4.7 10
0.01 10
1.22
±100
mV/mA
µF
µF
V
mV
1.4
VDD1 - 1
V
+2.05
2.05
1.0 VDD1 +
50mV
200 350
320
5
V/V
V/V
V
µA
2.0
0.8
0.2
±1
15
V
V
V
µA
pF
_______________________________________________________________________________________ 5

5 Page





MAX1080 arduino
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Detailed Description
The MAX1080/MAX1081 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 10-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1080/MAX1081.
Pseudo-Differential Input
The equivalent circuit of Figure 4 shows the MAX1080/
MAX1081s’ input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 1 and 2.
The MAX1080/MAX1081 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
sinusoidal signal at IN-, the input voltage is determined
by:
( )νIN= VINsin(2πft)
The maximum voltage variation is determined by:
( )max
dνIN
dt
=
VIN
2πf 1LSB
tCONV
=
VREF
210 tCONV
A 2.6Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / fSCLK). When a DC refer-
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
CHOLD as a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLD from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1/2 within the limits of 10-bit resolu-
tion. This action is equivalent to transferring a
12pF [(VIN+ - VIN-)] charge from CHOLD to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
CS 17
SCLK 18
DIN
SHDN
16
10
CH0 1
CH1 2
CH2 3
CH3 4
CH4 5
CH5 6
CH6 7
CH7 8
COM 9
REFADJ 12
REF 11
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
ANALOG
INPUT
MUX
OUTPUT
SHIFT
REGISTER
T/H
CLOCK
IN
10 + 2-BIT
SAR ADC
OUT
REF
+1.22V
REFERENCE
A 2.05
17k
+2.500V
MAX1080
MAX1081
14 DOUT
15 SSTRB
20 VDD1
19 VDD2
13 GND
GND
CAPACITIVE
REF DAC
INPUT
CH0 MUX
CH1
CHOLD
12pF
ZERO
COMPARATOR
CH2
CH3 CSWITCH*
CH4 6pF
RIN
800
CH5 TRACK
CH6
HOLD
AT THE SAMPLING INSTANT,
CH7 THE MUX INPUT SWITCHES FROM
COM THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
VDD1/2
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
*INCLUDES ALL INPUT PARASITICS
Figure 3. Functional Diagram
Figure 4. Equivalent Input Circuit
______________________________________________________________________________________ 11

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