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PDF MAX1002 Data sheet ( Hoja de datos )
| Número de pieza | MAX1002 | |
| Descripción | Low-Power / 60Msps / Dual / 6-Bit ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-1270; Rev 0; 7/97
EVAALVUAAILTAIOBNLEKIT
Low-Power, 60Msps, Dual, 6-Bit ADC
_______________General Description
The MAX1002 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual, parallel ADCs
are designed to convert in-phase (I) and quadrature
(Q) analog signals into two 6-bit offset-binary-coded
digital outputs at sampling rates up to 60Msps while
achieving typical integral nonlinearity (INL) and differ-
ential nonlinearity (DNL) of ±1/4LSB. The ability to
interface directly with baseband I and Q signals makes
the MAX1002 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
The MAX1002 input amplifiers feature true differential
inputs, a 55MHz -0.5dB analog bandwidth, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically 0.1dB gain, 1/4LSB offset, and 0.5° phase.
Dynamic performance is 5.85 effective number of bits
(ENOB) with a 20MHz analog input signal, or 5.78
ENOB with a 50MHz input signal.
The MAX1002 operates with a single +5V power supply
and provides TTL-compatible digital outputs. The device
is available in the commercial temperature range (0°C to
+70°C) and comes in a 36-pin SSOP package.
________________________Applications
____________________________Features
o ±1/4LSB INL and DNL, Typical
o 1/4LSB (typ) Channel-to-Channel Offset Matching
o 0.1dB Gain and 0.5° Phase Matching, Typical
o Internal Bandgap Voltage Reference
o Two Matched 6-Bit, 60Msps ADCs
o Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
o Internal Oscillator with Overdrive Capability
o 55MHz (-0.5dB) Bandwidth Input Amplifiers
with True Differential Inputs
o User-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
o Single-Ended or Differential Input Drive
o +5V Single Supply
o TTL Outputs
o 90Msps Upgrade with +3.3V CMOS-Compatible
Output Available (MAX1003)
______________Ordering Information
Direct Broadcast Satellite (DBS) Receivers
VSAT Receivers
Wide Local Area Networks (WLAN)
Cable Television Set-Top Boxes
PART
MAX1002CAX
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
36 SSOP
Pin Configuration appears at end of data sheet.
_________________________________________________________Functional Diagram
IOCC+
IOCC-
IIN+
INPUT
AMP
IIN- I
OFFSET
CORREC-
TION I
ADC
I
VREF
6
DATA
BUFFER
I
6
CLOCK
OUT
D0I–D5I
DCLK
GAIN
QIN+
QIN-
INPUT
AMP
Q
OFFSET
CORREC-
TION Q
BANDGAP
REFERENCE
VREF
ADC
Q
CLOCK
DRIVER
MAX1002
6
DATA
6
BUFFER
Q
TNK+
TNK-
DQ0–DQ5
QOCC+
QOCC-
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
For small orders, phone 408-737-7600 ext. 3468.
1 page  
Low-Power, 60Msps, Dual, 6-Bit ADC
______________________________________________________________Pin Description
PIN NAME
1 GAIN
2 IOCC+
3
4
5
6
7, 11, 12,
18, 19
8
9
10
13
14
15
16
IOCC-
IIN+
IIN-
VCC
GND
VCC
TNK+
TNK-
VCC
QIN-
QIN+
QOCC-
17
20–25
26, 28
27
29
30–35
36
QOCC+
DQ5–DQ0
VCCO
OGND
DCLK
DI0–DI5
VCC
FUNCTION
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).
Positive I-Channel Offset-Correction Compensation. Connect 0.22µF capacitor
for AC-coupled inputs (Figures 2, 3). Ground for DC-coupled inputs (Figures 4, 5).
Negative I-Channel Offset-Correction Compensation. Connect 0.22µF capacitor
for AC-coupled inputs (Figures 2, 3). Ground for DC-coupled inputs (Figures 4, 5).
I-Channel Noninverting Analog Input
I-Channel Inverting Analog Input
+5V ±5% Supply. Bypass with 0.01µF capacitor to GND (Pin 7).
Analog Ground
+5V ±5% Supply. Bypass with 0.01µF capacitor to GND (Pin 11).
Positive Oscillator/Clock Input
Negative Oscillator/Clock Input
+5V ±5% Supply. Bypass with 0.01µF capacitor to GND (Pin 12).
Q-Channel Inverting Analog Input
Q-Channel Noninverting Analog Input
Negative Q-Channel Offset-Correction Compensation. Connect 0.22µF capacitor
for AC-coupled inputs (Figures 2, 3). Ground for DC-coupled inputs (Figures 4, 5).
Positive Q-Channel Offset-Correction Compensation. Connect 0.22µF capacitor
for AC-coupled inputs (Figures 2, 3). Ground for DC-coupled inputs (Figures 4, 5).
Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB).
+5V ±5% Digital Supply. Bypass each with 47pF to OGND (Pin 27).
Digital Output Ground
Digital Clock Output. Frames the output data.
I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB).
+5V ±5% Supply. Bypass with 0.01µF to GND (Pin 19).
_______________Detailed Description
Converter Operation
The MAX1002 contains two 6-bit analog-to-digital con-
verters (ADCs), a buffered voltage reference, and oscil-
lator circuitry. The ADCs use a flash-conversion
technique to convert an analog input signal into a 6-bit
parallel digital output code. The MAX1002’s unique
design includes 63 fully differential comparators and a
proprietary encoding scheme that ensures no more
than 1LSB dynamic encoding error. The control logic
interfaces easily to most digital signal processors
(DSPs) and microprocessors (µPs) with +5V CMOS-
compatible logic interfaces. Figure 1 shows the
MAX1002 in a typical application.
Programmable Input Amplifiers
The MAX1002 has in-phase (I) and quadrature (Q) pro-
grammable-gain input amplifiers with a 55MHz
-0.5dB bandwidth and true differential inputs. To maxi-
mize performance in high-speed systems, each amplifier
has less than 5pF of input capacitance. The input ampli-
fier gain is programmed via the GAIN pin to provide
three possible input full-scale ranges (FSR) (Table 1).
Table 1. Input Amplifier Programming
GAIN
GND
Open
VCC
INPUT FULL-SCALE RANGE
(mVp-p)
500
250
125
_______________________________________________________________________________________ 5
5 Page 
Low-Power, 60Msps, Dual, 6-Bit ADC
__________________Pin Configuration
TOP VIEW
___________________Chip Information
TRANSISTOR COUNT: 6097
GAIN 1
IOCC+ 2
IOCC- 3
IIN+ 4
IIN- 5
VCC 6
GND 7
VCC 8
TNK+ 9
TNK- 10
GND 11
GND 12
VCC 13
QIN- 14
QIN+ 15
QOCC- 16
QOCC+ 17
GND 18
MAX1002
SSOP
36 VCC
35 DI5
34 DI4
33 DI3
32 DI2
31 DI1
30 DI0
29 DCLK
28 VCCO
27 OGND
26 VCCO
25 DQ0
24 DQ1
23 DQ2
22 DQ3
21 DQ4
20 DQ5
19 GND
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX1002.PDF ] | |
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