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PDF MAMUSM0008 Data sheet ( Hoja de datos )
| Número de pieza | MAMUSM0008 | |
| Descripción | Digital Switched Delay Line / 1.8 - 2.4 GHz | |
| Fabricantes | Tyco | |
| Logotipo |  |
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Digital Switched Delay Line,
1.8 - 2.4 GHz
V 1.00
Features
n 750 pS Dynamic Range, 50 pS Step Size
n BGA Package
n Parallel Control Interface
n Positive Control Logic
n Cascadable
n No off chip components required
Description
The M/A-COM MAMUSM0008 is a 0 to 750 pS variable
delay line controlled by 4 complementary bit pairs. It
provides the user with 50 pS delay step sizes for use in
standard wireless applications. The MAMUSM0008 is
particularly useful in providing time delay in the
cancellation loops of feed-forward amplifiers.
BGA Package
Absolute Maximum Ratings 1
Block Diagram
Parameter
Control Voltage
Maximum RF Input Power
Operating Temperature
Storage Temperature
Absolute Maximum
8.5V
+30 dBm
-40°C to +85°C
-55°C to +125°C
1. TA = +25°C (unless otherwise specified)
50 ps
100 ps
Electrical Specifications: TA = 25°C, Z0 = 50Ω
Parameter
Conditions
Frequency
1.8 - 2.4 GHz
Delay Line Control Range
—
Delay Line Control Step Size
—
Delay Step Accuracy
± 5 pS +5% of step size in pS
Output Return Loss
—
Input Return Loss
—
Input P1dB
—
Insertion Loss
—
Output IP3
PIN = 0 dBm, 5 MHz Spacing
Control Voltage
—
Control Current
—
Switching Speed
(50% TTL to 90% RF)
3V Control
Units
—
pS
pS
—
dB
dB
dBm
dB
dBm
V
µA
nS
Min.
—
0
—
—
15
15
27
5
36
2.7
2
—
200 ps
Typ.
—
—
50
—
20
20
—
—
38
3
20
72
400 ps
Max.
—
750
—
—
—
—
—
8
—
8.5
50
100
1 page  
Digital Switched Delay Line, 1.8 - 2.4 GHz
Control
Herein is described the control method for the
MAMUSM0008 Digital Delay Line. The information will
be aimed specifically at the use of the delay line mounted
on a M/A-COM test sample board. The same theory and
control scheme can be applied directly to the component by
itself.
This product allows the insertion of a variable electrical
delay between its two ports. The control consists of four
complimentary bit pairs (8 bits total). Each pair is given a
different letter, as shown in the table to the right:
MAMUSM0008
V 1.00
Delay Line
50 ps
100 ps
200 ps
400 ps
Associated Letter
A
B
C
D
Note that each delay line has a pair named as follows:
CTL_A1 and CTL_A2, CTL_B1 and CTL_B2,
CTL_C1 and CTL_C2, CTL_D1 and CTL_D2.
D2 D1 C2 C1 B2 B1 A2 A1
10101010
10101001
10100110
10100101
10011010
10011001
10010110
10010101
01101010
01101001
01100110
01100101
01011010
01011001
01010110
01010101
hex
decimal
state
ps delay
AA 170
0
0
A9 169 1 50
A6 166
2 100
A5 165
3 150
9A 154
4 200
99 153
5 250
96 150
6 300
95 149
7 350
6A 106 8 40
69 105
9 450
66 102 10 500
65 101 11 550
5A 90 12 600
59 89 13 650
56 86 14 700
55 85 15 750
The above table illustrates the method of controlling the bits for the desired delay in pico seconds. The hex and decimal
representations are included for programming purposes. “1” denotes 5 volts and “0” denotes 0 volts. A given delay line is set
when bits 2 and bit 1 are set to 0 and 1 respectively. The given delay line is bypassed when the bits 2 and 1 are set to 1 and 0
respectively.
The “GND” pin on the test board header must be connected to the DC supply ground.
Specifications subject to change without notice.
n North America: Tel. (800) 366-2266
n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298
n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020
Visit www.macom.com for additional data sheets and product information.
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MAMUSM0008.PDF ] | |
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