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PDF MACH4-96 Data sheet ( Hoja de datos )
| Número de pieza | MACH4-96 | |
| Descripción | High-Performance EE CMOS Programmable Logic | |
| Fabricantes | Lattice | |
| Logotipo |  |
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Lattice Semiconductor
1
FINAL
COM’L: -15
MACH 4 FAMILY
IND: -18
MACH4-96/96-15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
x 144 Pins in PQFP
x 96 Macrocells
x 15 ns tPD Commercial, 18 ns tPD Industrial
x 47.6 MHz fCNT
x 102 Inputs with pull-up resistors
x 96 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs
x 96 Flip-flops
x Up to 20 product terms per macrocell, with XOR
x Flexible clocking
— Four global clock pins with selectable edges
— Asynchronous mode available for each macrocell
x 3 MACH111SP-size blocks
x SpeedLocking™ for guaranteed fixed timing
x JTAG, 5-V, in-system programmable
x JTAG (IEEE 1149.1) boundary scan testing capability
x Input and output switch matrices for high routability
PLEASE NOTE: The MACH4-96/96 (M4-96/96) reflects a new nomenclature for the MACH® 4 Family.
This device is currently dual-marked with the MACH355 ordering part number. The dual-mark
scheme will facilitate design and manufacturing flows until we have completely phased in the new
M4-96/96 nomenclature. Please use the MACH355 data sheet (PID# 17467) as a reference.
GENERAL DESCRIPTION
The MACH4-96/96 (M4-96/96) is a member of Vantis’ high-performance EE CMOS MACH 4 family.
This device has approximately three times the macrocell capability of the popular MACH111SP,
with significant additional density and functional features.
The M4-96/96 consists of six PAL® blocks interconnected by a programmable central switch matrix.
The central switch matrix connects the PAL blocks to each other and to all input pins, providing a
high degree of connectivity between the PAL blocks. This allows designs to be placed and routed
efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix.
The input switch matrix provides input signals with alternative paths into the central switch matrix;
the output switch matrix provides flexibility in assigning macrocells to I/O pins.
Publication# 21535 Rev: A
Amendment/+1
Issue Date: November 1997
1
1 page  
VANTIS
ORDERING INFORMATION
Commercial Products
Vantis programmable logic products for commercial applications are available with several ordering options. The order
number (Valid Combination) is formed by a combination of:
FAMILY TYPE
M4 = MACH 4 Family (5-V VCC)
DEVICE NUMBER
96 = 96 Macrocells
I/O
/96 =144-pin Package
M4 -96 /96 -15 Y C
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
Y = 144-Pin Plastic Quad Pack
(PQR144)
SPEED
-15 = 15 ns tPD
Valid Combinations
MACH4-96/96-15
YC
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local Vantis
sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
MACH4-96/96-15 (Com’l)
5
5 Page 
VANTIS
The output switch matrix allows macrocells to be connected to any of several I/O cells within a
PAL block. This provides high flexibility in determining pinout, and allows design changes that will
not affect pinout.
In the MACH 4 devices, each PAL block has twice as many macrocells as I/O cells. The MACH 4
output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in
combinations according to Figure 5. Each I/O cell can choose from eight macrocells; each
macrocell has a choice of four I/O cells.
I/O Macro-
Cell cell
I/O Macro-
cell cell
I/O Macro-
cell cell
Macro-
cell
I/O
cell
I/O
cell
Macro-
cell
Macro-
cell
MUX
I/O
Cell
I/O Macro-
cell cell
I/O Macro-
cell cell
I/O Macro-
cell cell
a. Macrocell drives one of 3 I/Os
Figure 5.
b. I/O can choose one of 8 macrocells
21535A-5
MACH4-96/96 Output Switch Matrix
The I/O Cell
The I/O cell (Figure 6) in the M4-96/96 consists of a three-state buffer and an input flip-flop. The
I/O cell is driven by one of the macrocells, as selected by the output switch matrix. Each I/O cell
can take its input from one of eight macrocells. The three-state buffer is controlled by an individual
product term. The direct I/O signal is available to the input switch matrix, and can be used
if desired.
MACH4-96/96-15
11
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