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PDF MACH130-20JC Data sheet ( Hoja de datos )
| Número de pieza | MACH130-20JC | |
| Descripción | High-Density EE CMOS Programmable Logic | |
| Fabricantes | Lattice | |
| Logotipo |  |
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FINAL
COM’L: -15/20
IND: -18/24
MACH130-15/20
High-Density EE CMOS Programmable Logic
Lattice Semiconductor
DISTINCTIVE CHARACTERISTICS
84 Pins
64 Macrocells
15 ns tPD Commercial
18 ns tPD Industrial
66.6 MHz fCNT
70 Inputs
GENERAL DESCRIPTION
The MACH130 is a member of the high-performance
EE CMOS MACH 1 family. This device has approxi-
mately six times the logic macrocell capability of the
popular PAL22V10 without loss of speed.
The MACH130 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
64 Outputs
64 Flip-flops; 4 clock choices
4 “PAL26V16” Blocks
Pin-compatible with MACH131, MACH230,
MACH231, MACH435
The MACH130 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type or T-type to help reduce the
number of product terms. The register type decision can
be made by the designer or by the software. All
macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the
macrocell can be used, which frees up the I/O pin for use
as an input.
Publication# 14131 Rev. H Amendment /0
Issue Date: April 1995
1 page  
ORDERING INFORMATION
Industrial Products
Programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
MACH 130 -18 J I
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
DEVICE NUMBER
130 = 64 Macrocells, 84 Pins
SPEED
-18 = 18 ns tPD
-24 = 24 ns tPD
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
J = 84-Pin Plastic Leaded
Chip Carrier (PL 084)
Valid Combinations
MACH130-18
MACH130-24
JI
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult your local sales office to confirm availability
of specific valid combinations and to check on newly
released combinations.
MACH130-18/24 (Ind)
5
5 Page 
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 2.0 V VCC = 5.0 V, TA = 25°C
VOUT= 2.0 V f = 1 MHz
Typ Unit
6 pF
8 pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description
-18
Min Max
-24
Min Max
Unit
tPD Input, I/O, or Feedback to Combinatorial
Output (Note 3)
18 24 ns
Setup Time from Input, I/O, or Feedback
tS to Clock
D-type
T-type
12
13.5
16
17
ns
ns
tH Hold Time
tCO Clock to Output (Note 3)
tWL
Clock Width
tWH
Maximum
fMAX Frequency
(Note 1)
External Feedback 1/(tS + tCO)
Internal Feedback (fCNT)
0
LOW
HIGH
D-type
T-type
D-type
T-type
7.5
7.5
40
38
53
44
0 ns
12 14.5 ns
10 ns
10 ns
32 MHz
30 MHz
38 MHz
34.5 MHz
tAR
tARW
tARR
tAP
tAPW
tAPR
tEA
tER
No Feedback
1/(tWL + tWH)
Asynchronous Reset to Registered Output
Asynchronous Reset Width (Note 1)
Asynchronous Reset Recovery Time (Note 1)
Asynchronous Preset to Registered Output
Asynchronous Preset Width (Note 1)
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 3)
Input, I/O, or Feedback to Output Disable (Note 3)
66.5 50
MHz
24 30 ns
18 24
ns
12 18
ns
24 30 ns
18 24
ns
12 18
ns
18 24 ns
18 24 ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit, for test conditions.
3. Parameters measured with 32 outputs switching.
MACH130-18/24 (Ind)
11
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