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PDF MACH120-12 Data sheet ( Hoja de datos )
| Número de pieza | MACH120-12 | |
| Descripción | High-Performance EE CMOS Programmable Logic | |
| Fabricantes | Lattice | |
| Logotipo |  |
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Lattice Semiconductor
1
FINAL
COM’L: -12/15
MACH 1 & 2 FAMILIES
IND: -18
MACH120-12/15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
x 68 Pins in PLCC
x 48 Macrocells
x 12 ns tPD Commercial, 18 ns tPD Industrial
x 77 MHz fCNT Commercial
x 48 I/Os; 4 dedicated inputs; 4 dedicated inputs/clocks
x 48 Outputs
x 48 Flip-flops; 4 clock choices
x 4 “PALCE26V12” blocks
x SpeedLocking™ for guaranteed fixed timing
x Pin-compatible with the MACH221
GENERAL DESCRIPTION
The MACH120 is a member of the high-performance EE CMOS MACH ® 1 family. This device
has approximately five times the logic macrocell capability of the popular PALCE22V10 without
loss of speed.
The MACH120 consists of four PAL® blocks interconnected by a programmable switch matrix.
The switch matrix connects the PAL blocks to each other and to all input pins, providing a high
degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed
and routed efficiently.
The MACH120 macrocell provides either registered or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type
to help reduce the number of product terms. The register type decision can be made by the
designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell
is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin
for use as an input.
Publication# 14129 Rev: J
Amendment/0
Issue Date: November 1997
1 page  
ORDERING INFORMATION
Industrial Products
Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
MACH 120 –18 J I
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
DEVICE NUMBER
120 = 48 Macrocells, 68 Pins
SPEED
–18 = 18 ns tPD
Valid Combinations
MACH120-18
JI
OPERATING CONDITIONS
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
J = 68-Pin Plastic Leaded
Chip Carrier (PL 068)
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local Vantis
sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
6 MACH120-18 (Ind)
5 Page 
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
Ambient Temperature
With Power Applied . . . . . . . . . . . . . -55°C to +125°C
Device Junction Temperature . . . . . . . . . . . . . +150°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . . -0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = -40°C to +85°C) . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
INDUSTRIAL OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges
Parameter
Symbol
Parameter Description
Test Conditions
Min Typ Max Unit
VOH Output HIGH Voltage
IOH = -3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
V
VOL Output LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
0.5 V
VIH Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
VIL Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8 V
IIH
IIL
IOZH
IOZL
ISC
ICC
Input HIGH Current
VIN = 5.25 V, VCC = Max (Note 2)
Input LOW Current
VIN = 0 V, VCC = Max (Note 2)
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3)
Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4)
-30
10 µA
-10 µA
10 µA
-10 µA
-130 mA
85 mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded,
enabled, and reset.
12 MACH120-18 (Ind)
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