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PDF MA3690 Data sheet ( Hoja de datos )
| Número de pieza | MA3690 | |
| Descripción | 1553B Bus Controller/Remote Terminal | |
| Fabricantes | Dynex | |
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Replaces June 1999 version, DS3587-4.0
MA3M6A93609/01/1//33
1553B Bus Controller/Remote Terminal
DS3587-5.0 January 2000
The MA3690/1 chip set has three modes of operation:
remote terminal, bus controller, and passive monitor It has a
dual bus capability, requires minimum support hardware /
software and is implemented on a radiation hard, CMOS/SOS
process. For applications requiring access to Terminal Flag, a
48-Pin DIL MA3693 is available as an alternative to the
MA3690.
As a remote terminal, the MA3690/1 is fully compatible with
Mil-Std-1553B. The chip set obtained SEAFAC approval in
December 1987. All options and mode commands specified by
the Mil Std are implemented Full and meaningful use is made
of status word bits and a comprehensive bit word is provided.
A unique mechanism has been incorporated that allows
the subsystem to declare illegal commands legal, and vice
versa, before the chip set services the command. It should be
noted that use of this mechanism is optional and that the
system defaults to normal operation if the option is not
required. The chip set is easily interfaced to subsystem
memory and is sufficiently flexible to ensure compatibility with
a wide range of microprocessors.
As a bus controller the MA3690/1 has the ability to initiate
all types of 1553B transfer on either of the two buses An
instruction word is set up by the subsystem, prior to
transmission, which contains details of transfer type and bus
selection. Four bits of the instruction word have been used to
specify the conditions under which the chip set will generate a
subsystem interrupt. The most significant bits of the instruction
word have been used to specify the conditions under which the
chip set will perform an automatic retry and the number of
retries to be carried out (max. 3). At the end of each instruction
execution cycle, the chip set writes a report word into the
subsystem memory; the contents of which give the subsystem
an indication of the degree of success of the transfer.
The bus controller may be used in either of two
configurations, i.e. single shot or table driven.
In the single shot configuration, the controller is under
direct control from the subsystem (processor). In table driven
configuration, the controller is given greater autonomy to
execute a table of instructions held in either ROM or RAM.
As a passive monitor, the chip set will monitor all bus
activity and pass any associated information to the subsystem.
As the name implies, in this mode of operation, the chip set is
truly passive and will not reply to command instructions.
FEATURES
s Radiation Hard to 1MRads (Si)
s High SEU Immunity, Latch-Up Free
s CMOS-SOS Technology
s All Inputs and Outputs Fully TTL or CMOS Compatible
s Military Temperature Range -55 to +125°C
s Dual Bus Capability
s Minimal Subsystem Interface
s Powerful Bus Control Facility
s Complete Remote Terminal Protocol
s SEAFAC Approved
SIGNAL DESCRIPTIONS
All signals are TTL compatible unless stated otherwise. An
‘N’ at the end of the signal name denotes an active low signal.
SUPPLIES
VDD
5 volts positive supply
VSS
Ground
CLOCK INPUTS
CK12
12MHz clock
BUS INTERFACE LINES
PDIN0
Input
Positive threshold exceeded on bus 0.
NDIN0
Input
Negative threshold exceeded on bus 0.
TXEN0N Output
Transmit enable for driver on bus 0.
PDOUT0N Output
Positive Manchester data for driver on bus 0.
1/41
1 page  
MA3690/1/3
Four bits of the Instruction word (bits 10-7) define
conditions under which the terminal will generate an interrupt
to the subsystem (IRQN). Note that the generation of IRQN will
only take place after any selected retry conditions have been
exhausted.
The interrupt conditions which may be selected can be
categorised as follows:
1. Interrupt if no response - the terminal will generate an
interrupt if the RT does not respond.
2. Interrupt if Status bit set - the terminal will generate an
interrupt if a received status word has a bit set other
than in the RT address field or if the wrong RT
responds.
3. Interrupt Always - the terminal will generate an
interrupt regardless of whether the message was
successful or not.
4. Interrupt if word error - the terminal will generate an
interrupt if a word encoding or word count error
occurs.
Retry Count
The two most significant bits of the instruction word specify
the number of retries to be carried out when a retry condition
has been detected. (Maximun 3 given by code 11)
RECEIVE COMMAND WORD
The receive command word is addressed when CODENN
and C1 are both low and R/WN and C0 are both high. This
word is the command word which will be transmitted for a BC
to RT transfer or as the first command word of an RT to RT
transfer.
Note: This word should be set to 1111 HEX if the message
code is 000 or 100, or if the Function Code is not 00.
TRANSMIT COMMAND WORD
In all of the above cases, the terminal will generate a 250ns
pulse on IRQN and enter the halted state. This will occur after
the Report sequence has been executed.
Note the INCADRN will not be produced.
Retry Condition
Code Definition
The transmit command word is addressed when CODENN
and C0 are both low and R/WN and C1 are both high. This
word is the command word which will be transmitted for an RT
to BC transfer or as the second command word of an RT to RT
transfer.
Note: This word should be set to 1111 HEX if the message
code is 001 or 101, or if the Function Code is not 00.
001 Retry if error
010 Retry if status bit set
100 Retry if busy set
Three bits of the Instruction word (bits 13-11) are used as
flags to specify conditions under which the terminal will
execute automatic message retries until the retry number
count is zero. The retry flags are involved with the following
conditions:
1. Retry if error - this includes a no-status response, a
word encoding error, or a wrong word count from a
responding RT.
2. Retry if Status bit set - an automatic retry will take
place if a received status word has a bit set, other
than in the RT address field, or if the wrong RT
responds.
3. Retry if Busy - this is a specific check for the setting of
the Busy bit in a responding RT’s status word.
DATA POINTER WORD
The data pointer word is addressed when CODENN is low
and C0, C1 and R/WN are all high. This word is intended as a
base address pointer to the subsystem data store thus
specifying where any data words associated with the current
instruction should be stored or retrieved from. As such, this
word is not read into the terminal itself but is merely transferred
from the Instruction Store to a suitable external address latch.
(The BUFENN signal is therefore inactive during this transfer).
The remaining two bits of the Instruction word specify the
number of message retries which the Bus Controller will
attempt automatically. A code of 00 specifies no retries, a code
of 11 specifies the maximum of three retries. The retries are in
addition to the initial message transmitted, hence a message
may be transmitted four times in total, if not successful. Note
that if the condition which is being tested becomes invalid, the
retry sequence will discontinue on the next message with the
Bus Controller completing execution of the message in the
relevant manner.
5/41
5 Page 
MA3690/1/3
SUBSYSTEM INTERFACE
The terminal / subsystem interface consists of a 16 bit
bidirectional data highway and a number of control lines, many
of which are of optional use. The subsystem lines have been
arranged such as to allow a simple shared store technique to
be readily implemented but sufficient flexibility has been
designed to allow optimisation of the interface for a particular
subsystem design.
The terminal contains a 16 regisiter, called BIT word, which
records message errors and terminal status information. The
entire BIT word contents are reset by power up initialisation or
a legal mode command to reset remote terminal. The
conditions for the setting of the BIT, and any additional reset
conditions are given for each signal.
The contents of the BIT word register shall not be altered
by any of the following legal mode commands. Transmit
Status Word (TSW), Transmit Last Command (TLC) and
Transmit BIT Word (TBW).
REMOTE TERMINAL MODE
Transmitter Timeout Error
On initialisation, the RT address, address parity and
broadcast enables are loaded from the subsystem via the data
highway, Figure 4. The subsystem status bits are also loaded
in a similar manner when required, Figure 5.
This terminal uses two distinct methods for dealing with
non mode data and mode data. In the first, a busy request /
acknowledge handshake is used to ensure no data transfer
takes place when the subsystem is busy thus ensuring no
addressing / data conflict of the main data store. Mode data,
however, may be transferred even if the subsystem has
declared itself busy. This represents a departure from previous
chipset philosophy.
The validation of a data transfer also depends on data type.
For non mode data, a data transfer request / acknowledge
handshake is used to transfer each data word to or from the
subsystem (both RT and BC) with a good block received
(GBRN) denoting a correct transfer. For mode data, a mode
data transfer (MDTN) is used to signal a mode data word with
correct transfer being denoted by mode data received
(MDRN). Thus, dependant on application, the l/O signals may
be significantly reduced.
An RT subsystem interface signal transfer is shown in
Figure 6.
BIT WORD
0
0
TX Timeout Bus 1
TX Timeout Bus 0
Terminal Flag Inhibited
0
Bus 1 Shutdown
Bus 0 Shutdown
Illegal Broadcast
Word Count High
Word Count Low
Illegal Command
Illegal T/R Bit
Loop Test Failure
SS Handshake Failure
TX Timeout Error
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
This BIT shall be set to logic one if transmitter timeout
occurs while the terminal is tranmitting. In addition, if the
terminal is issued with a legal mode command to Initiate Self
Test (code 00011) this bit shall be set if the range transmitter
timeout mechanism does not operate within the of 660 µs to
800 µs.
Subsystem Handshake Failure
This bit shall be set to logic one if the subsystem does not
acknowledge a terminal request to transfer a data word in time
for the transfer to take place correctly.
Loop Test Failure
At all times while the terminal is transmitting the relevant
receiver circuitry checks for an absence of transmission or any
sync, Manchester, parity or contiguity error in the terminals
transmission. This bit shall be set to logic one if any of these
error conditions are detected.
Illegal T/R Bit
This bit shall be reset to logic zero by the reception of any
valid command word with the exception TSW,TLC and TBW.
This bit shall be set to logic one if a valid mode command is
received with a transmit/receive (T/R) bit opposite to that
specified by MIL-STD-1553B.
Illegal Command
This bit shall be reset to logic zero by the reception of any
valid command word with exceptions TSW, TLC and TBW.
This bit shall be set to logic one if any of the following
conditions arise:
(a) The ILLEGAL COMMAND line to the subsystem
status latch is low at the time when INCMD goes
active low.
(b) A valid mode command is received with a reserved
mode code and the ALLOW CODE line to the
subsystem staus latch is high at the time when
INCMD goes low.
(c) An illegal transitter shutdown mode command is
received.
11/41
11 Page | ||
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| PDF Descargar | [ Datasheet MA3690.PDF ] | |
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