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PDF MA31753 Data sheet ( Hoja de datos )
| Número de pieza | MA31753 | |
| Descripción | DMA Controller (DMAC) For An MA31750 System | |
| Fabricantes | Dynex | |
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Replaces June 1999 version, DS3825-4.0
MAM3A137175533
DMA Controller (DMAC) For An MA31750 System
DS3825-5.0 January 2000
The MA31753 Direct Memory Access Controller (DMAC) is
a peripheral interface circuit design primarily for use with the
MA31750 microprocessor. Each DMAC provides up to four
independant, prioritised channels each of which can perform
DMA transfers between memory and/or I/O devices using the
MA31750 bus. Each channel has its own programmable
internal priority and can be masked under program control.
Further, individual channels have their own associated status
and control words enabling an individual channel to be re-
programmed without disturbing transfers which may be taking
place on other channels. Three basic transfer modes are
available:
Direct Memory to I/O peripheral transfers,
Direct I/O to Memory transfers,
Memory to Memory transfers,
I/O to I/O transfers.
The MA31753 interfaces directly to the MA31750 bus,
directly supporting on chip parity generation and supporting
expanded memory via an MA31751 MMU with either 1 MWord
(1750A mode) or 16MWords (1750B mode) of logical memory.
The MA31753 uses System memory to hold address and
count information for each transfer. Once this information has
been prepared by the processor the DMAC can conduct a
number of transfers without further processor intervention.
FEATURES
s Radiation Hard CMOS SOS Technology
s Four Independant DMA Channels
s MIL-STD-1750A or B Operation in an MA31750 System
s Capable of Processor Independant Table Driven
Operation
s Memory to Memory, I/O to Memory, Memory to I/O and
I/O to I/O Transfers Supported
s Masking of Individual Channel DMA Requests
s Simple MA31750 Bus Interface
s Single Word, Double Word or Multi-Word Transfers for
each of the DMA Channels
s Cascade Interface Allows for Channel Expansion
s Programmable Channel Priority
s Parity Checking Available
AS[0:3]
PS[0:3]
PB[0:3]
DREQN[0:3]
DACKN[0:3]
DMAE
D[0:16]
A[0:15]
CSN
CLK
RESETN
DSN
AS
MION
OIN
RDWN
RDN
WRN
RDYN
GRANTN
REQN
LOCKN
DMAKN
SEC/FIRSTN
DONEN
AKRDN
AKWRN
EXADEN
PEN
MPROEN
MA31753
DMAC
INTRN
REQINN
GEINN
GEOUTN
DPARN
DTON
VDD
VSS
Figure 1: Pin Connections - Top View
1/30
1 page  
MA31753
3.10 SOFTWARE PROGRAMMING
DMA requests can be generated in software by writing the
CRQP bit in the Channel Status register. If the channel is
active, the DMA will then request bus control. If the DREQN
signal on that channel is not active, the DMA finishes the cycle
as soon as the memory is ready. There is no handshaking with
the IO port. DACKN is deasserted when the memory is ready.
If DREQN is asserted but is masked, the handshaking is active
and operates normally.
Interrupts can be generated in software by setting either a
channel EOT flag or any error flag. This can only be done
when the DMA is in PEND_CHAIN mode. If an error flag is set,
the device goes straight to ERROR mode. If the EOT flag is
set, the device looks as if it has completed the transfer. It will
then just sit and wait for the EOT flag to be cleared before
entering IDLE mode. If both flags are set simultaneously, the
device remains in PEND_CHAIN mode. Setting an error flag
when EOT is set resets EOT and the device goes to ERROR
mode. Setting EOT when an error flag is set clears the error
and the DMA sits in the finish transfer mode.
3.11 CASCADING DMA CONTROLLERS
DMA controllers are cascaded in series. For each DMA
added, an extra 4 channels become available. To cascade the
devices, the strobes, control signals and address and data
busses are connected in parallel. Of the bus arbitration
signals, LOCKN and GRANTN should be connected in parallel
and REQINN, GEINN and GEOUTN shoudl be daisy-chained.
INTRN and PEN can either be ORed together with external
glue logic or input to seperate CPU interrupts. Figure 3 shows
the cascade connections.
Bus
Arbiter
GRANTN
REQN REQINN
DMAC 1
GEOUTN
44
REQN
DMAC 2
GEINN
44
Figure 3: Cascading DMA Controllers
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5 Page 
MA31753
6.0 PIN DESCRIPTIONS
A[0:15]
I/O A[0] is the most significant bit of this logical address bus. This bus is an input during cycles not assigned to the
DMA and is driven during DMA cycles.
PB[0:3]
O Used in 1750B mode only, this bus provides DMA page bank information which addresses up to 8M of memory.
The bus is tri-stated during cycles not assigned to the DMA.
AS[0:3]
O This bus indicates the current address state of the DMA controller. It is tri-stated during cycles not assigned to the
DMA.
PS[0:3]
O This bus indicates the current process state of the DMA controller. It is tri-stated during cycles not assigned to the
DMA.
D[0:16]
I/O D[0] is the most significant bit of the data bus. During DMA cycles, data is input on read cycles and output on write
cycles. D[16] is the parity bit. Odd or even parity is set in the configuration word. Parity is not used during DMA
writes to memory.
CLK I Input clock signal
RESETN
I This active low signal resets the DMA.
CSN
I When low, access to read and write the DMA internal registers is enabled.
AS I/O AS high indicates the presence of a valid address on the address bus. This signal is an input on cycles not
assigned to the DMA.
DSN
I/O When low, data strobe indicates the presence of data on the data bus. This signal is an input on cycles not assigned
to the DMA.
MION
I/O If high, this signal indicates that the current cycle is accessing memory space. If low, the current cycle is
accessing IO space. Is an input during cycles not assigned to the DMA.
RDWN
I/O During DMA cycles, this signal goes high to indicate read cycles and low to indicate write cycles. It is an input
during non-DMA cycles.
OIN O During DMA cycles, this signal goes high to indicate operand cycles and low to indicate instruction cycles. It is tri-
stated during non-DMA cycles.
RDN
O This active low read strobe is tri-stated on non-DMA cycles.
WRN
O This active low write strobe is tri-stated on non-DMA cycles.
RDYN
I/O This signal goes active low to indicate that the current bus cycles can be terminated. It is an output on cycles
addressing the DMA internal registers, input on cycles controlled by the DMA and is tri-stated during all other
cycles.
LOCKN
O This signal is driven low during the first bus cycle of a double word transfer. It should be used by the bus arbiter to
'lock' bus control to the DMA. It is tri-stated during cycles not assigned to the DMA.
REQN
O Always driven, this signal goes low to indicate that the DMA requests the bus.
GRANTN
I Sampled by the DMA on negative CLK edges, this signal goes low to indicate that the DMA has bus control.
DMAKN
O This output is driven active low by the DMA when it has bus control. It is tri-stated on cycles not assigned to the
DMA.
DONEN
O This signal is pulsed low for one CLK cycle when any of the four DMA channels reaches an 'end of transfer'
condition.
REQINN
I Sampled by the DMA on negative CLK edges, a low on this input indicates that a cascaded, lower priority DMA is
requesting the bus. This input should be tied high in a single DMA system.
GEINN
I This active low signal is used to qualify the GRANTN signal for cascaded DMA devices. This signal should be tied
low on the first DMA of the chain.
GEOUTN O This active low output indicates that a lower priority DMA will be granted the bus when the GRANTN signal is
asserted low from the arbiter. It is used to cascade DMA devices by connecting to the GEINN pin of the next DMA.
INTRN
O This active low interrupt request signal pulses low when an 'end of transfer' or an internal error condition are
detected.
PEN
I The DMA samples PEN on AS falling. If an error condition is sampled, the transfer on the DMA channel is stopped
and the CLE bit is set in the Channel Status Register.
DMAE
I An active high input to indicate that the DMA is enabled. If this input is low, internal requests are supressed, there is
no response to external requests and REQINN is gated out internally.
DPARN
I A low on this signal resets and disables checking of the parity bit (D[16])
DTON
I A low on this signal resets and disables the bus fault timeout circuitry.
MPROEN
I This input is sampled on AS falling when the DMA has bus control. If an active low is sampled, the transfer stops
on the channel concerned and the CAE (addressing error) bit is set in the channel status register. An interrupt may
be generated.
EXADEN
I This input is sampled on AS falling when the DMA has bus control. If an active low is sampled, the transfer stops
on the channel concerned and the CAE (addressing error) bit is set in the channel status register. An interrupt may
be generated.
DREQN[0:3] I Sampled by the DMA on negative CLK edges, a low on this bus initiates a DMA transfer providing the
corresponding channel is correctly set up and is not masked. When the pin is pulled high, the ongoing bus cycle
will terminate.
DACKN[0:3] O During a transfer, the DMA drives the relevant channel acknowledge low to indicate that the DMA is ready for the
data. The low to high transition at the end of the cycle is initiated by the condition DREQN high and RDYN low.
SEC/FIRSTN O A high indicates that the first word in a transfer is occuring. A low indicates that the second word in a double word
transfer is occuring.
AKRDN
O This active low strobe indicates that the DMA is driving the data bus.
AKWRN
O This active low strobe indicates that the DMA is inputting data from the data bus.
11/30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MA31753.PDF ] | |
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