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PDF MA31751 Data sheet ( Hoja de datos )
| Número de pieza | MA31751 | |
| Descripción | Memory Management & Block Protection Unit | |
| Fabricantes | Dynex | |
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Replaces June 1999 version, DS4083-2.0
MAM3A137175511
Memory Management & Block Protection Unit
DS4083-3.0 January 2000
The MA31751 Memory Management Unit/Block Protect
Unit (MMU/BPU) is an optional chip which may be used to
expand the capabilities of the MA31750.
User configurable, the MA31751 can perform as an MMU,
a BPU or both MMU and BPU, conforming to MIL-STD-1750A
and 1750B. MMU mapping and BPU protection for 1M words
of memory is provided by the internal memory. Up to 16
MA31751 devices can be used to give 16M words of logical
mapped onto 8M words of physical address space with
protection in 1750B mode.
The MA31751 is designed to have a simple interface to
both the CPU and the system bus with the minimal number of
control lines. This reduces board space and simplifies system
design.
The MA31751 traps the MMU and BPU XIO commands to
program and read the logical to physical mapping and memory
access control. This provides simple memory management as
defined by the MIL-STD-1750.
FEATURES
s MlL-STD-1750A/B Compatible
s Radiation Hard CMOS/SOS Technology
s User Configurable as Either a Memory Management Unit
(MMU) or a Block Protect Unit (BPU) or Both
s Memory Management Unit Configuration
• 1 MWord Physical Address Space
• Access Lock and Key of 4K-Word Blocks
• Write/Execute Protection of 4K-Word Blocks
s Block Protect Unit Configuration
• Protection of 1K-Word Blocks
• Global Memory Write Protection During Initialisation
s Direct Memory Access Support
CPU
Busses
Bus
Control
Chip
Control
Signals
System
Signals
A[0:15]
AS[0:3]
PS[0:3]
OIN
MION
RDWN
ASIN
DSN
D[0:16]
PRPEN
MPROEN
GLPE
DMAKN
CSN
HITMISSN
BPUVALIDN
EAS
RESETN
VDD
GND
EA[0:10]
MA31751
System
Faults
Figure 1: Chip Control Signals
1/17
1 page  
MA31751
2.0 TIMING CONSIDERATIONS
3.2 MPROEN
2.1 MMU TIMINGS
To enable a fast page register look-up time, the MMU has
two fast translation cache registers. These hold the address
translation information on the 4K memory page which is
currently being accessed. When the CPU has control of the
system, one cache register is for operand transfers and one for
instruction transfers, as these often occur in different pages.
The appropriate translation cache register is chosen by the
operand/instruction (OIN) signal from the CPU. When a DMA
has system control, the caches operate as Read/Write caches,
the appropriate cache being selected by the RDWN signal.
When either an instruction/read or an operand/write crosses a
page boundary, one wait state may be added whilst the
translation cache register is updated from internal memory.
This system minimises the MMU overhead.
This signal is always low when ASIN is low. On a memory
access, with an MMU only present it stays low until the
address translation is validated. If the translation is erroneous,
it stays low, causing a machine cycle time-out. If a BPU is
present with the MMU, an erroneous translation causes the
output to stay low. If the translation is correct, MPROEN will
still stay low until the BPU check has completed. If there is no
block protection set, MPROEN goes high, allowing the cycle to
proceed. If the block protection is set, MPROEN stays low and
the cycle times out. In a BPU only system, MPROEN indicates
whether or not the protection bit is set for the address being
accessed.
In a 1750B system with both an MMU and BPU present,
MPROEN may glitch between the translation validation and
the protection check (as the MMU and BPU functions may be
on different devices). In this case, MPROEN should be gated
with BPUVALIDN being low before being input to the CPU.
2.2 BPU TIMINGS
A similar caching system is employed in the BPU section
of the MA31751 to allow more rapid detection of access
violations. If the physical address crosses a 16K block
boundary, then one wait state may be added.
Different combinations of cache hits and misses give
different access times if the MA31751 is acting as both an
MMU and a BPU. If the logical address (from the CPU) gives
an MMU cache hit, the physical address is looked-up from the
translation cache register (operand or instruction, depending
on OIN). If the physical address gives a cache hit, the
protection for the block is looked-up in the BPU cache register.
This situation (both hits) gives the fastest access time. The
access time is a maximum if both logical and physical
addresses give cache misses.
3.0 OUTPUTS FROM THE MA31751
3.1 PRPEN
3.3 BPUVALIDN
BPUVALIDN falls to indicate that the output from the BPU
is valid. If no BPU is present, BPUVALIDN remains high.
4.0 PIN DESCRIPTIONS
A description of each pin function appears in Figure 6. The
acronym is presented first, followed by its function and
description. Timing characteristics of each of the functions are
shown in section 6.
All CMOS compatible signals are protected by an
Electrostatic Discharge (ESD) protection circuit. Throughout
this data sheet, active low signals are denoted either by
placing a bar over the signal name,or by following the signal
name with an “N” suffix, e.g.,DSN.
All unused inputs should be connected to their inactive
state and should not be allowed to float.
This signal goes active low if a parity error occurs on a
memory access, ie. there is a parity error in the MMU page
register. There is no parity checking on XIO cycles, (this
should be covered by the processor).
5/17
5 Page 
MA31751
ASIN
(From CPU)
DSN
A0-A15
AS0-3
MION
RDWN
OIN
DMAKN
5
(From CPU)
27
6
28
EA0:10
12
13
11
EAS (From MMU)
14
From MMU with cache hit
30
PRPEN
Figure 13: MMU Address Translation (Cache Hit)
ASIN (From
CPU)
DSN
A0-A15
AS0-3
MION
RDWN
OIN
DMAKN
5
27
EA0:10
EAS (From MMU)
PRPEN
(From
CPU)
15
12
14
6
28
11
30
Figure 14: MMU Address Translation (Cache Miss)
11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MA31751.PDF ] | |
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