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PDF MA31750 Data sheet ( Hoja de datos )
| Número de pieza | MA31750 | |
| Descripción | High Performance MIL-STD-1750 Microprocessor | |
| Fabricantes | Dynex | |
| Logotipo |  |
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Replaces July 1999 version, DS3748-7.0
MAM3A137175500
High Performance MIL-STD-1750 Microprocessor
DS3748-8.0 January 2000
The Dynex Semiconductor MA31750 is a single-chip
microprocessor that implements the full MIL-STD-1750A
instruction set architecture, or Option 2 of Draft MIL-STD-
1750B. The processor executes all mandatory instructions and
many optional features are also included. Interrupts, fault
handling, memory expansion, Console, timers A and B, and
their related optional instructions are also supported in full
accordance with MIL-STD-1750.
The MA31750 offers a considerable performance increase
over the existing MAS281. This is achieved by using a 32-bit
internal bus structure with a 24 x 24 bit multiplier and 32-bit
ALU. Other performance-enhancing features include a 32-bit
shift network, a multi-port register file and a dedicated address
calculation unit.
The MA31750 has on-chip parity generation and checking
to enhance system integrity. A comprehensive built-in self-test
has also been incorporated, allowing processor functionality to
be verified at any time.
Console operation is supported through a parallel interface
using command/data registers in l/O space. Several discrete
output signals are produced to minimise external logic.
Control signals are also provided to allow inclusion of the
MA31750 into a multiprocessor or DMA system.
The processor can directly access 64KWords of memory in
full accordance with MIL-STD-1750A. This increases to
1MWord when used with the optional MA31751 memory
management unit (MMU). 1750B mode allows the system to
be expanded to 8MWord with the MMU.
Parity
Bus
arb.
Bus
Control Address Data
IO control
C0
C1
DOUT
Register
file
IC A
X
Address
BR generator
IB
IA
rap
CLK
ebf
uAddr
Microcode ROM
Sequencer
Microcode control
words to other blocks
uData
ALU
Qshift
sc
Multiplier
ir
Shift network
abort
Interrupt
controller
R bus
S bus
Ints
Faults
INTAKN
BUSFAULTN
mov bf
aluv
Flags
Y bus
Figure 1: Architecture
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MA31750
3.2. INSTRUCTION EXECUTION
Once initialisation has been completed, the processor will
begin instruction execution. Instruction execution is
characterised by a variety of operations, each is one machine
cycle in duration (two or more system CLK periods).
Depending on the instruction being executed at the time, these
operations include: (1) internal CPU cycles, (2) instruction
fetches, (3) operand transfers, and (4) input/output transfers.
Instruction execution may be interrupted at the end of any
individual machine cycle by an interrupt or Console request.
Internal cycles are always two CLK periods long, whilst the
other cycle types are a minimum of two CLK periods -
extendable by inserting waitstates. In all cycles except internal
cycles, RDN, WRN, DSN and AS strobes are produced to
control the transfer and latching of data and address around
the system.
Cycle Type RD/WRN O/IN
Internal Cycle H
L
Instruction
Fetch
H
L
Operand Read H
Operand Write L
IO Read
H
IO Write
L
H
H
H
H
M/ION
H
H
H
H
L
L
Description
Used to perform all CPU data manipulation operations where bus
activity is not required.
Used to keep the instruction pipeline full with instructions and/or their
postwords. At least one instruction is always ready for execution when
the preceding instruction is completed. During jump and branch
instruction execution the pipeline is refilled by two consecutive
instruction fetches starting at the new instruction location. It is also
refilled as part of interrupt request processing.
Used to read in data from the external system and to write results to the
system.
Input/Output transfers utilize the MIL-STD-1750 XIO and VIO
instructions. RD/WN defines the direction of the transfer. IO transfers
may be divided into three groups; those commands which are
implemented internally by the CPU, those commands which are
implemented by external system hardware and those commands
defined as illegal by MIL-STD-1750A and B.
Figure 7: External Cycle Types
3.3. IO OPERATION
The MA31750 supports a 64KWord addressing space
dedicated to IO control and communication in accordance with
MIL-STD-1750. The control line MION is asserted low when
accessing IO space (see figure 7 above for other strobe
states). One of the two commands XIO or VIO is used to
specify both data for the transfer and the port address (referred
to as an XIO Command in 1750). The CPU contains logic
which decodes all internally supported XIO commands and
generates the control signals necessary to carry out the
commanded action. In addition, the validity of a command not
implemented internally is verified. Figure 20c identifies the XIO
commands which are internally supported by the MA31750.
3.4. INTERRUPT AND FAULT HANDLING
3.4.1. STATUS WORD (SW)
Figure 8 depicts the status register format. This 16-bit word
is divided into four, 4-bit sections. Three of these sections [AS,
PS and, (1750B mode) PB] are control bits for implementing
expanded memory with an external MMU. The fourth section,
CS, is used to hold the carry, positive, zero and negative
condition flags set by the result of the previous arithmetic
operation.
0 3 4 7 8 11 12 15
CS R (PB) PS
AS
Field Bits
Description
CS 0
1
2
3
CONDITION STATUS
C- Carry from an addition or no
borrow from a subtraction.
P- Result > 0
Z- Result = 0
N- Result < 0
R 4-7
PB
PS 8-11
RESERVED (=0) in 1750A mode
Page Bank Select in 1750B mode
PROCESSOR STATE:
(a)- Memory access to key code
(b)- Priviledged instruction enable
AS 12-15 ADDRESS STATE:
Page register sets for expanded
memory addressing.
Figure 8: Status Word Format
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5 Page 
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Status Word (SW)
Instruction Counter (IC)
Fault Register (FT)
Fault Mask (1750B only)
Pending Interrupt (PI)
Interrupt Mask (MK)
Timer A
Timer A reset (1750B only)
Timer B
Timer B reset (1750B only)
Trigger-Go Reset Register
Configuration
MA31750
4.8. MIL-STD-1750 DATA TYPES
The MA31750 fully supports 16-bit fixed-point single-
precision, 32-bit fixed-point double-precision, 32-bit floating-
point, and 48-bit extended precision floating- point data types.
Figure 16 depicts the formats of these data types.
All numerical data is represented in two’s complement
form. Floating-point numbers are represented by a fractional
two’s complement mantissa with an 8-bit two’s complement
exponent. All floating-point operands are expected to be
normalised. If not normalised, the results from an instruction
are not defined.
4.9. MIL-STD-1750 ADDRESSING MODES
The MA31750 supports the eight basic addressing modes
specified in MIL-STD-1750A. These addressing modes are
depicted in Figure 18 and are defined below. In binary
operations one operand is assumed to be in a register
(specified as part of the opcode) whilst the second operand
(the Derived Operand, DO) is taken from a source which is
dependent upon the addressing mode, see figure 17. Many
adddressing modes may be specified as indexable: the index
register may be any of the general purpose registers R1-R15
(if 0 is specified then the non-indexable form is used). For
Base Relative addressing modes the first operand is fixed as
part of the instruction (either R0 for Double Integer operations,
or R2 for Single Integer operations).
4.10. MEMORY ADDRESSING CAPABILITY
In accordance with MIL-STD-1750A, the MA31750 can
access a 64KWord address space directly. With the addition of
a single external Dynex Semiconductor MA31751 chip,
configured as a Memory Management Unit (MMU), this
address space may be expanded to 1MWord (1750A mode) or
8MWord (1750B mode). The MA31751 data sheet gives
further information on the MMU/BPU chip and on the memory
management scheme employed. Note that whilst one MMU
can be used to provide the full range of physical addresses to
the system memory, the logical addressing capability may also
be expanded by adding further MMU devices up to a maximum
of 16.
Figure 14: Register Set Model
Register(s)
R0
R2
R3-R11
R12-R15
R15
Notional Use or Restriction on Use
Cannot be used as an index register
With R1: Implied register in Double mode Base Relative addressing
Implied register in Single mode Base Relative addressing
General purpose
Base relative registers
Stack pointer in PSHM and POPM operations
Figure 15: General Register Usage
11/42
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MA31750.PDF ] | |
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