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PDF MA17503 Data sheet ( Hoja de datos )
| Número de pieza | MA17503 | |
| Descripción | Radiation Hard MIL-STD-1750A Interrupt Unit | |
| Fabricantes | Dynex | |
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Replaces June 1999 version, DS3566-4.0
MAM1A715750033
Radiation Hard MIL-STD-1750A Interrupt Unit
DS3566-5.0 January 2000
The MA17503 Interrupt Unit is a component of the MAS281
chip set. Other chips in the set include MA17501 Execution Unit
and the MA17502 Control Unit. Also available is the peripheral
MA31751 Memory Management/Block Protection Unit. The
lnterrupt Unit, in conjunction with these additional chips,
implements the full MIL-STD-1750A Instruction Set
Architecture.
The MA17503 - consisting of the Pending Interrupt
Register, Mask Register, Interrupt Priority Encoder, Fault
Register, Timer A, Timer B, Trigger-Go Counter, Bus Fault
Timer, and DMA interface - handles all interrupt fault, and DMA
interfacing, in addition to providing all three hardware timers.
The Interrupt Unit also implements 26 of the MIL-STD-1750A
specified l/O commands. Table 1 provides brief signal
definitions.
The MA17503 is offered in dual-in-line, flatpack or leadless
chip carrier packaging. Screening and packaging options are
described at the end of this document.
BLOCK DIAGRAM
FEATURES
s Mil-Std-1750A Instruction Set Architecture
s Full Performance over Military Temperature Range (-55°C
to +125°C)
s Radiation Hard CMOS/SOS Technology
s Interrupt Handler
• 9 User Interrupt Inputs
• Pending Interrupt Register
• Interrupt Mask Register
• Interrupt Priority Encoder
s Fault Handler
• 8 User Faults Inputs
• Fault Register
s Timers
• Timer A
• Timer B
s Trigger-Go
s DMA Interface
s Interface Discretes
• Normal Power-Up
• Start-Up ROM Enable
• Configuration Word Enable
s Implements 26 MIL-STD-1750A Specified l/O Commands
s MAS281 Integrated Built-ln Self Test
s TTL Compatible System Interface
1/34
1 page  
MA17503
Anti-repeat logic between the FT and Pl prevents latching
more than a single interrupt into the Pl before the user interrupt
service routine has cleared the FT. The microcoded interrupt
service routine reads the interrupt priority vector from the
Interrupt Unit and clears the serviced interrupt from the Pl. At
this point the Pl is ready to latch another interrupt into this bit.
When this microcoded service routine acts on a level 1
interrupt, it clears the Pl bit 1, but the FT maintains the
interrupting fault bit(s). Therefore, a level 1 interrupt would be
latched again if there were no anti-repeat logic to prevent a
never ending loop of interrupts from occurring.
Interrupts are serviced at the end of the currently executing
instruction if not masked and if interrupts are enabled. System
software servicing level 1 interrupts must clear the FT via the
RCFR internal l/O command at some point in the routine to
allow subsequent faults to latch a level 1 interrupt request. A
non-destructive read of the FT is provided by the internal I/O
command RFR, but this command should be used carefully.
2.5 INTERVAL TIMERS
The Interrupt Unit contains both MIL-STD-1750A 16-bit
interval timers, A and B. The TCLK input is synchronized with
SYNCLKN and increments Timer A once a TCLK period. Timer
B is incremented by the synchronized TCLK divided by 10.
Timer A overflow sets Pl bit 7 and Timer B overflow sets Pl bit 9.
The timers are controlled via the l/O command decode logic, or
they can be disabled via the DTlMERN input.
2.6 WATCHDOG TIMERS
The Interrupt Unit contains two watchdog timers, Trigger-
Go and Bus Fault. The Bus Fault timer assures timely
completion of all AD Bus cycles by terminating bus cycles over
two TCLK (maximum, minimum one TCLK period) periods in
duration. This function is automatic, but can be disabled by
DTON low. FT bit 5 or 8 is set for terminated l/O transfers or
memory transfers, respectively, when the Bus Fault timer
expires.
The Trigger-Go timer is an autonomous 16-bit ripple
counter incremented by TGCLK. Upon power-up, the Trigger-
Go timer begins to count. The GO l/O command resets the
timer, thus preventing it from overflowing and causing TGON to
drop low. The DTIMERN input prevents the Trigger-Go timer
from incrementing.
2.7 DMA CONTROL INTERFACE
The DMA control interface logic is contained in the Interrupt
Unit. The interface is composed of the three signals: DMAE,
DMARN, and DMAKN. If the interface is enabled, an internal
l/O command raises DMAE high to indicate the MAS281’s
readiness to accept DMA transfer requests (DMARN low). A
subsequent low on DMARN causes the lU to respond with
DMAKN low. DMAKN low halts the processor and places all AD
Bus and bus control lines in the high-impedance state. Control
is returned to the MAS281 when DMARN is pulled high again.
DTIMERN is the user available way to disable the DMA
interface.
2.8 INTERNAL I/O COMMAND DECODE LOGIC
The Interrupt Unit implements the 26 MIL-STD-1750A
specified l/O command functions listed in Table 2. The lU also
decodes an additional 386 commands that are implemented in
the MMU(BPU) and the two Status Word XlO commands that
are handled in microcode for AD Bus control. The lU continually
monitors AD Bus traffic. When M/lON is low, the lU latches the
information present on the AD Bus during the address portion
of the bus cycle. This information is subsequently decoded and
creates the appropriate control signals to perform the l/O
command function.
2.9 MICROCODE DECODE LOGIC
The microcode decode logic can be split into command and
control functions. Microcode instruction bits 4, 5 and 6 are
decoded as commands for the FT, the interrupt interface, the
DMA interface, and the discrete output signal, NPU. The
microcode command interface is enabled when lNTREN is
pulled low and is disabled during DMA and the Hold state.
Microcode bits 5 and 6 provide control of DDN during memory
read and write cycles, and external l/O cycles.
Operation
Output
Set Fault Register
Set Interrupt Mask
Clear Interrupt Request
Enable Interrupts
Dlsable Interrupts
Reset Pending Interrupt
Set Pending Interrupt Reglster
Reset Normal Power Up Discrete
Write Status Word
Enable Start Up ROM
Disable Start up ROM
Direct Memory Access Enable
Direct Memory Access Disable
Timer A Start
Timer A Halt
Output Timer A
Reset Tngger-Go
Timer B Start
Timer B Halt
Output Timer B
Command Mnemonic
Code (Hex)
0401
2000
2001
2002
2003
2004
2005
200A
200E
4004
4005
4006
4007
4008
4009
400A
400B
400C
400D
400E
SFR
SMK
CLIR
ENBL
DSBL
RPI
SPI
RNS
WSW
ESUR
DSUR
DMAE
DMAD
TAS
TAH
OTA
GO
TBS
TBH
OTB
Input
Read Configuration Word
Read Fault Register Wlthout Clear
Read Interrupt Mask
Read Pending Interrupt Reglster
Read Status Word
Read and Clear Fault Reylster
Input Timer A
Input Tlmer B
8400
8401
A000
A004
A00E
A00F
C00A
C00E
RCW
RFR
RMK
RPIR
RSW
RCFR
ITA
ITB
5/34
5 Page 
MA17503
Each of the nine user interrupt inputs is buffered by a falling-
edge detector to prevent repeat latching of requests held low
longer than the first SYNCLKN high-to-low transition. An
interrupt request input must go back to the high state before
request on that input can be detected.
Command
Load Fault Register From AD Bus
M04, M05, M06
001
Read Interrupt Priority Vector
Onto AD Bus
010
Raise Normal Power-up Discrete
011
Disable l/O Control of DMA lnterface
100
Enable l/O Control of DMA Interface
101
Table 5: Interrupt Unit Microcode Commands
The output of the Pl register is continually ANDed with the
output of the MK register (level 0 interrupt is not maskable). If
interrupts are enabled, and an unmasked interrupt is pending,
the Interrupt Request (IRN) output to the Control Unit is
asserted. This occurs when one or more interrupts are latched
and unmasked. The unmasked pending interrupts are output to
the priority encoder where the highest priority pending interrupt
is encoded as a 4-bit vector.
After the currently executing MIL-STD-1750A instruction is
completed, the Control Unit checks the state of the lRN input. If
IRN is asserted, a branch is made to the microcode interrupt
service routine. During this routine, the priority encoder's 4-bit
vector is read into the Execution Unit, where the vector is used
to calculate the appropriate interrupt linkage and service
pointers (Table 6). When the EU reads the interrupt priority
vector from the lU, the interrupt being serviced is cleared from
the Pl. If no other interrupts are pending, this also causes the
IRN signal to be deactivated.
4.4 FAULT SERVICING
Eight external fault inputs are provided to the interrupt unit.
A low on any of these inputs is latched into the FT register at the
high-to-low transition of SYNCLKN. The capture of one or more
of these faults immediately sets pending interrupt level 1
(machine error) of the Pl.
Anti-repeat logic between the FT and Pl prevents latching
more than a single interrupt into the Pl before the user interrupt
service routine has cleared the FT. The microcoded interrupt
service routine reads the interrupt priority vector from the
Interrupt Unit and clears the serviced interrupt from the Pl. At
this point the Pl is ready to latch another interrupt into this bit.
When this microcoded service routine acts on a level 1
interrupt, it clears the Pl bit 1, but the FT maintains the
interrupting fault bit(s). Therefore, a level 1 interrupt would be
latched again if there was no anti-repeat logic to prevent a
never ending loop of interrupts from occurring.
Interrupts are serviced at the end of the currently executing
instruction if not masked and if interrupts are enabled. System
software servicing level 1 interrupts must clear the FT via the
RCFR internal l/O command at some point in the routine to
allow subsequent faults to latch a level 1 interrupt request. A
non-destructive read of the FT is provided by the internal I/O
command RFR, but this command should be used carefully.
Faults caused by a low on EXADEN, MPROEN, or Bus
Fault Timer expiration (FT 0, 5, 8) require that the currently
executing MlL-STD-1750A instruction be aborted. In order to
accomplish this, the latching of faults 0, 5, or 8 causes the
lnterrupt Unit to assert the instruction abort (PIFN) output to
both the Execution Unit and the Control Unit Faults 0, 5, and 8
are not latched during DMA cycles or the Hold state (CDN low).
Interrupt
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Functlon
Power Down
Machine Error
User 0
Floating Point Overflow
Fixed Point Overflow
Executive Call
Floating Point Underflow
Timer A
User 1
Timer B
User 2
User 3
l/O 1
User 4
I/O 2
User 5
Priority(1)
Level
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Maskable
No
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Dlsablllty
No
No
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note: (1) Level 0 has highest priority, level 15 lowest.
Table 6: Interrupt Vector Assignments
Linkage
Pointer
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
Service
Pointer
21
23
25
27
29
2B
2D
2F
31
33
35
37
39
3B
3D
3F
11/34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MA17503.PDF ] | |
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