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Número de pieza | M95320 | |
Descripción | 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock | |
Fabricantes | ST Microelectronics | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de M95320 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! M95640
M95320
64Kbit and 32Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
s Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
s Single Supply Voltage:
– 4.5 to 5.5V for M95xxx
– 2.5 to 5.5V for M95xxx-W
– 1.8 to 5.5V for M95xxx-R
s 10MHz, 5MHz or 2MHz clock rate (depending
on ordering options)
s 5ms or 10ms Write Time (depending on
ordering options)
s Status Register
s Hardware Protection of the Status Register
s BYTE and PAGE WRITE (up to 32 Bytes)
s Self-Timed Programming Cycle
s Adjustable Size Read-Only EEPROM Area
s Enhanced ESD Protection
s More than 100,000 or 1 million Erase/Write
Cycles (depending on ordering options)
s More than 40 Year Data Retention
Figure 1. Packages
8
1
PDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
November 2003
TSSOP14 (DL)
169 mil width
1/39
1 page M95640, M95320
SUMMARY DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 8192 x 8 bit (M95640), and 4096 x 8
bit (M95320).
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
Figure 2. Logic Diagram
Figure 3. DIP and SO Connections
M95xxx
S1
Q2
8 VCC
7 HOLD
W3
6C
VSS 4
5D
AI01790D
VCC
D
C
S
W
HOLD
M95xxx
VSS
Q
AI01789C
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
Figure 4. TSSOP14 Connections
M95xxx
S1
Q2
14 VCC
13 HOLD
NC 3
12 NC
NC 4
11 NC
NC 5
10 NC
W6
9C
VSS 7
8D
AI02346C
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
2. NC = Not Connected
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
5/39
5 Page MEMORY ORGANIZATION
The memory is organized as shown in Figure 8.
Figure 8. Block Diagram
HOLD
W
S
C
D
Q
Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
Data
Register
M95640, M95320
Status
Register
Size of the
Read only
EEPROM
area
1 Page
X Decoder
AI01272C
11/39
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet M95320.PDF ] |
Número de pieza | Descripción | Fabricantes |
M95320 | 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock | ST Microelectronics |
M95320-DRE | 32-Kbit serial SPI bus EEPROM | STMicroelectronics |
M95320-R | 32 Kbit and 64 Kbit Serial SPI bus EEPROMs | STMicroelectronics |
M95320-W | 32 Kbit and 64 Kbit Serial SPI bus EEPROMs | STMicroelectronics |
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