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PDF IDT5T9050 Data sheet ( Hoja de datos )
| Número de pieza | IDT5T9050 | |
| Descripción | 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IDT5T9050 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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IDT5T9050
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™ JR.
INDUSTRIALTEMPERATURERANGE
IDT5T9050
FEATURES:
• Optimized for 2.5V LVTTL
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 300 (max)
• High speed propagation delay < 1.8ns. (max)
• Up to 200MHz operation
• Very low CMOS power levels
• Hot insertable and over-voltage tolerant inputs
• 1:5 fanout buffer
• 2.5V VDD
• Available in TSSOP package
DESCRIPTION:
The IDT5T9050 2.5V single data rate (SDR) clock buffer is a single-ended
input to five single-ended outputs buffer built on advanced metal CMOS
technology. TheSDRclockbufferfanoutfromasingleinputtofivesingle-ended
outputs reduces the loading on the preceding driver and provides an efficient
clock distribution network. Multiple power and grounds reduce noise.
APPLICATIONS:
• Clock and signal distribution
FUNCTIONAL BLOCK DIAGRAM
GL
G
OUTPUT
CONTROL
Q1
OUTPUT
CONTROL
Q2
A
OUTPUT
CONTROL
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2002 Integrated Device Technology, Inc.
1
OCTOBER 2002
DSC-5958/17
1 page  
IDT5T9050
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.
INDUSTRIALTEMPERATURERANGE
A
GL
tPLH
G
tPGD
Qn
tP G E
VIH
VTH
VIL
VIH
VTH
VIL
VIH
VTH
VIL
VOH
VTH
VOL
Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their G signal to avoid this problem.
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IDT5T9050.PDF ] | |
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