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PDF IDT5993A-5Q Data sheet ( Hoja de datos )

Número de pieza IDT5993A-5Q
Descripción PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™
IDT5993A
FEATURES:
• 3 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Output frequency: 3.75MHz to 100MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 5V with TTL outputs
• 3 skew grades:
IDT5993A-2: tSKEW0<250ps
IDT5993A-5: tSKEW0<500ps
IDT5993A-7: tSKEW0<750ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 46mA IOL high drive outputs
• Low Jitter: <200ps peak-to-peak
• Outputs drive 50terminated lines
• Available in QSOP package
DESCRIPTION:
The IDT5993A is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5993A has six programmable skew
outputs and two zero skew outputs. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
FUNCTIONAL BLOCK DIAGRAM
V C C Q /P E
REF
FB
PLL
3
FS
G N D /sO E
Skew
S e le ct
33
1 F 1 :0
Skew
S e le ct
33
2 F 1 :0
Skew
S e le ct
33
3 F 1 :0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2001 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
SEPTEMBER 2001
DSC 5844/1

1 page




IDT5993A-5Q pdf
IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
INPUT TIMING REQUIREMENTS
Symbol
Description(1)
tR, tF Maximum input rise and fall times, 0.8V to 2V
tPWC Input clock pulse, HIGH or LOW
DH Input duty cycle
REF Reference Clock Input
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Min. Max. Unit
— 10 ns/V
3 — ns
10 90 %
3.75 100 MHz
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5993A-2
IDT5993A-5
IDT5993A-7
Symbol Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
FNOM
tRPWH
tRPWL
tU
VCO Frequency Range
REF Pulse Width HIGH(1)
REF Pulse Width LOW(1)
Programmable Skew Time Unit
See PLL Programmable Skew Range and Resolution Table
3— —
3 — — 3 ——
3— —
3 — — 3 ——
See Skew Selection Table for Output Pairs
tSKEWPR
tSKEW0
tSKEW1
Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3)
Zero Output Skew (All Outputs)(1,4,5)
Output Skew
(Rise-Rise, Fall-Fall, Same Class Outputs)(1,3)
— 0.05 0.2
— 0.1 0.25
— 0.25 0.5
— 0.1 0.25 —
— 0.25 0.5 —
— 0.6 0.7 —
0.1 0.25
0.3 0.75
0.6 1
tSKEW2 Output Skew
(Rise-Fall, Divided-Divided)(1,6)
— 0.5 1 — 0.5 1.2 — 0.5 1.5
tSKEW3 Output Skew
(Rise-Rise, Fall-Fall, Different Class Outputs)(1,6)
— 0.25 0.5
— 0.5 0.7 — 0.7 1.2
tSKEW4 Output Skew
(Rise-Fall, Nominal-Divided)(1,2)
— 0.5 0.9 — 0.5 1 — 1.2 1.7
tDEV
tPD
tODCV
Device-to-Device Skew(1,2,7)
REF Input to FB Propagation Delay(1,9)
Output Duty Cycle Variation from 50%(1)
0.25
1.2
0
0
0.75 — — 1.25 — — 1.65
0.25 0.5 0
0.5 0.7 0
0.7
1.2 1.2 0
1.2 1.2 0
1.2
tPWH Output HIGH Time Deviation from 50%(1,10)
——
tPWL Output LOW Time Deviation from 50%(1,11)
——
tORISE Output Rise Time(1)
0.15 1
tOFALL Output Fall Time(1)
0.15 1
tLOCK PLL Lock Time(7)
——
tJR Cycle-to-Cycle Output Jitter
RMS
——
Peak-to-Peak — —
2
——
2.5 — —
3
1.5 — — 3 — — 3.5
1.2 0.15 1
1.5 0.15 1.5 2.5
1.2 0.15 1
1.5 0.15 1.5 2.5
0.5 — — 0.5 — — 0.5
25
——
25 — — 25
200 — — 200 — — 200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. For IDT5993A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.35ns Max.
6. There are two classes of outputs: Nominal (multiple of tU delay), and Divided (3Qx only in Divide-by-2 or Divide-by-4 mode).
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
9. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
10. Measured at 2V.
11. Measured at 0.8V.
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