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PDF IDT54FCT810BT Data sheet ( Hoja de datos )

Número de pieza IDT54FCT810BT
Descripción FAST CMOS BUFFER/CLOCK DRIVER
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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Integrated Device Technology, Inc.
FAST CMOS
BUFFER/CLOCK DRIVER
IDT54/74FCT810BT/CT
FEATURES:
• 0.5 MICRON CMOS technology
• Guaranteed low skew < 600ps (max.)
• Very low duty cycle distortion < 700ps (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: –32mA IOH, 48mA IOL
• Two independent output banks with 3-state control
– One 1:5 Inverting bank
– One 1:5 Non-Inverting bank
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, CERPACK and
LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT810BT/CT is a dual bank inverting/ non-
inverting clock driver built using advanced dual metal CMOS
technology. It consists of two banks of drivers, one inverting
and one non-inverting. Each bank drives five output buffers
from a standard TTL-compatible input. The IDT54/
74FCT810BT/CT have low output skew, pulse skew and
package skew. Inputs are designed with hysteresis circuitry
for improved noise immunity. The outputs are designed with
TTL output levels and controlled edge rates to reduce signal
noise. The part has multiple grounds, minimizing the effects of
ground inductance.
FUNCTIONAL BLOCK DIAGRAMS
PIN CONFIGURATIONS
OEA
INA
OEB
INB
5
OA1-OA5
5
OB1-OB5
3103 drw 01
VCC
1
20 VCC
OA1
2
19 OB1
OA2
3
18 OB2
OA3
GND
OA4
OA5
4
P20-1
17
5
D20-1
SO20-2
16
6
SO20-7
SO20-8
15
&
7
E20-1
14
OB3
GND
OB4
OB5
GND
8
13 GND
OEA
9
12 OEB
INA 10
11 INB
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
3103 drw 02
INDEX
OA3
GND
OA4
OA5
GND
32
20 19
4 1 18
5 17
6
L20-2
16
7 15
8 14
9 10 11 12 13
OB2
OB3
GND
OB4
OB5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
9.4
LCC
TOP VIEW
3103 drw 03
OCTOBER 1995
DSC-4646/3
1

1 page




IDT54FCT810BT pdf
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
VCC 7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500
50pF
500
RT CL
3103 drw 04
ENABLE AND DISABLE TIME
SWITCH POSITION
Test
Switch
Disable LOW
Closed
Enable LOW
Disable HIGH
Open
Enable HIGH
DEFINITIONS:
3103 lnk 07
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
TEST WAVEFORMS
PACKAGE DELAY
INPUT
tPLH
OUTPUT
3V
1.5V
tPHL
0V
VOH
2.0V
1.5V
0.8V VOL
tR tF
3103 drw 05
OUTPUT SKEW (ALL BANKS) - tSK2(o)
OUTPUT SKEW (SAME BANK) - tSK1(o)
3V
INPUT
tPLH1
tPHL1
1.5V
0V
VOH
OUTPUT 1
tSK1(o)
tSK1(o)
1.5V
VOL
VOH
OUTPUT 2
tPLH2
tPHL2
1.5V
VOL
tSK1(o) = |tPLH2 - tPLH1| or |tPHL2 - tPLH1|
3103 drw 06
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK2(o)
tSK2(o)
tPHL2
tPLH2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
PULSE SKEW - tSK(p)
INPUT
OUTPUT
tPLH
tPHL
tSK(p) = |tPHL - tPLH|
3V
1.5V
0V
VOH
1.5V
VOL
tSK2(o) = |tPHL2 - tPLH1| or |tPLH2 - tPHL1| 3103 drw 07
3103 drw 08
PACKAGE SKEW - tSK(t)
ENABLE AND DISABLE TIMES
INPUT
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tPD1a
tPD1b
tSK2(o)
tSK2(o)
tPD2a
tPD2b
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
tSK(t) = |tPD2a - tPD1a| or |tPD2b- tPD1b|
Package 1 and Package 2 are same device type and speed grade
NOTES:
3103 drw 09
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f 1.0MHz; tF 2.5ns; tR 2.5ns
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
t PZL
SWITCH
CLOSED
t PZH
SWITCH
OPEN
DISABLE
3.5V
1.5V
t PHZ
t PLZ
0.3V
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
3103 drw 10
9.4 5

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