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PDF IDT54FCT543D Data sheet ( Hoja de datos )
| Número de pieza | IDT54FCT543D | |
| Descripción | FAST CMOS OCTAL LATCHED TRANSCEIVER | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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®
Integrated Device Technology, Inc.
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
IDT54/74FCT543
IDT54/74FCT543A
IDT54/74FCT543C
FEATURES:
• IDT54/74FCT543 equivalent to FAST™ speed
• IDT54/74FCT543A 25% faster than FAST
• IDT54/74FCT543C 40% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 64mA (commercial), 48mA (military)
• Separate controls for data flow in each direction
• Back-to-back latches for storage
• CMOS power levels (1mW typ. static)
• Substantially lower input current levels than FAST
(5µA max.)
• TTL input and output level compatible
• CMOS output level compatible
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT543/A/C is a non-inverting octal trans-
ceiver built using an advanced dual metal CMOS technology.
These devices contain two sets of eight D-type latches with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must
be LOW in order to enter data from A0–A7 or to take data from
B0–B7, as indicated in the Function Table. With CEAB LOW,
a LOW signal on the A-to-B Latch Enable (LEAB) input makes
the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both LOW, the 3-state B output buffers
are active and reflect the data present at the output of the A
latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
FUNCTIONAL BLOCK DIAGRAMS
DQ
LE
A0
DETAIL A
QD
LE
B0
A1
A2
A3
A4
A5
A6
A7
OEBA
CEBA
LEBA
DETAIL A x 7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.17
B1
B2
B3
B4
B5
B6
B7
OEAB
CEAB
LEAB
2614 drw 01
MAY 1992
DSC-4602/3
1
1 page  
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT543
IDT54/74FCT543A
IDT54/74FCT543C
Symbol
tPLH
tPHL
tPLH
tPHL
Parameter
Propagation Delay
Transparent Mode
An to Bn or Bn to An
Propagation Delay
LEBA to An, LEAB to Bn
Com’l.
Mil.
Com’l.
Mil.
Com’l.
Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
CL = 50pF 2.5 8.5 2.5 10.0 2.5 6.5 2.5 7.5 2.5 5.3 2.5 6.1 ns
RL = 500Ω
2.5 12.5 2.5 14.0 2.5 8.0 2.5 9.0 2.5 7.0 2.5 8.0 ns
tPZH Output Enable Time
tPZL OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
2.0 12.0 2.0 14.0 2.0 9.0 2.0 10.0 2.0 8.0 2.0 9.0 ns
tPHZ Output Disable Time
tPLZ OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
2.0 9.0 2.0 13.0 2.0 7.5 2.0 8.5 2.0 6.5 2.0 7.5 ns
tSU Set-up Time, HIGH or LOW
An or Bn to LEBA or LEAB
3.0 — 3.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns
tH Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
tW LEBA or LEAB Pulse Width
LOW
2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns
5.0 — 5.0 — 5.0 — 5.0 — 5.0 — 5.0 — ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2513 tbl 07
7.17 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IDT54FCT543D.PDF ] | |
Hoja de datos destacado
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| IDT54FCT543AT | FAST CMOS OCTAL LATCHED TRANSCEIVER | Integrated Device |
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